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CMX850
CML Microcircuits
COMMUNICATION SEMICONDUCTORS
D/850/6 December 2003
Communications Controller
Provisional Issue
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Features 8051 C with internal 8K XRAM and up to 35 GPIO 64K address, bank switchable to many Mbytes Interfaces for external RAM, LCD controller, etc. V.22bis, V.22, V.23, V.21 (and Bell) integral modem DTMF/Tones transmit and receive Line and Phone differential amplifiers Dual clocks with separate Xtals CLI/CIDCW Tones detection and generation Line reversal / Ring detection Off-hook detector Low power operation Advanced power management features Watchdog timer Real-time clock and alarm function Bootstrap ROM to reprogram external FLASH Customised memory versions available from CML
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Standard 8051 UART and timers 2 input 10-bit A to D converter Keyboard encoder (16 x 8 matrix max) 2 x low-power PWM outputs Programmable Tx DTMF twist Dedicated low-power FSK Rx for CLI Small footprint: 100-pin LQFP Applications SMS and ADSI terminals Telemetry and meter reading systems Security systems Feature phones Routers EPOS terminals E-Mail and Internet appliances
1.1
Brief Description
This IC combines an extended function CMX860 with a full-function 8051 microcontroller (including UART and timer/counters), and has 8kbytes of RAM to form a powerful communications processor. Extended addressing offers page mode access to 4Mbytes of external FLASH memory. A 32.768kHz clock system allows a very low power interrupt-driven real time clock, watchdog timer and keyboard encoder. The device also includes a separate CAS tone detector and FSK receiver, two low power PWM outputs and a multiplexed 2-input 10-bit A to D converter with auto-convert and threshold detect. Advanced low power and sleep modes, including the ability to work from an on-chip RC oscillator, aid low battery consumption.
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CONTENTS Section 1.0 1.1 1.2 1.3 1.4 Page Features and Applications ..................................................................1 Brief Description..................................................................................1 Block Diagram .....................................................................................5 Signal List ............................................................................................6 External Components........................................................................ 10 1.4.1 Ring Detector Interface ......................................................... 12 1.4.2 Hook Detector Interface ........................................................ 13 1.4.3 RESETN pin........................................................................... 13 1.4.4 Local BOOT ROM.................................................................. 14 1.4.5 Line Interface......................................................................... 14 Microcontroller Core ......................................................................... 17 1.5.1 Special Function Register Memory Map .............................. 18 1.5.2 Dual Data Pointer .................................................................. 18 1.5.2.1 DPTR Registers (DPL/DPH DPL1/DPH1) ...... 18 1.5.2.2 Data Pointer Select Register (DPS) .............. 19 1.5.3 I/O Ports................................................................................. 20 1.5.3.1 Port Data Registers (P0-P5) .......................... 21 1.5.3.2 Port Direction Registers (P0DIR-P5DIR) ...... 21 1.5.3.3 Port Open-Drain Registers (P1OD-P5OD) .... 21 1.5.3.4 Port Res Pull-up Registers (P1RES-P5RES) 22 1.5.4 Memory Interface................................................................... 23 1.5.4.1 Memory Control Register (MEMCON) .......... 23 1.5.5 Interrupts ............................................................................... 25 1.5.5.1 Interrupt Enable Registers (IE, IE_1)............ 26 1.5.5.2 Interrupt Priority Registers (IP, IP_1) ........... 26 1.5.5.3 Interrupt Control Registers (ICON1A/B)....... 27 1.5.6 Oscillator and Power Management ...................................... 28 1.5.6.1 Oscillator Control Register (OSCCON) ........ 30 1.5.6.2 Speed Control Register (SPDCON) .............. 32 1.5.6.3 Speed Control Exit Register (SPXMASK)..... 33 1.5.6.4 Power Down Exit Register (PDXMASK) ....... 33 1.5.6.5 Power Control Register (PCON) ................... 34 1.5.7 Pulse Width Modulators ....................................................... 34 1.5.7.1 PWM Control Register (PWMCON)............... 35 1.5.7.2 PWM Data Registers (PWM1, PWM2) ........... 35 1.5.8 Analog to Digital Converter .................................................. 36 1.5.8.1 ADC Control Registers (ADCCON1/2) .......... 36 1.5.8.2 ADC Buffer Registers (ADCBUFL/H) ............ 40 1.5.8.3 ADC Threshold Registers (ADCTHRL/H) ..... 41 1.5.9 C-BUS Controller................................................................... 41 1.5.9.1 C-BUS Control Register (CBUSCON) ........... 42 1.5.9.2 C-BUS Buffer Register (CBUSBUF).............. 43 1.5.10 Keyboard Encoder ................................................................ 44 1.5.10.1 Keyboard Control Register (KBCON)........... 44 1.5.10.2 Keyboard Status Register (KBSTAT) ........... 45 1.5.10.3 Keyboard Buffer Register (KBBUF).............. 46
1.5
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1.5.11 Watchdog Timer.................................................................... 47 1.5.11.1 Watchdog Control Register (WDTCON) ....... 47 1.5.11.2 Watchdog Load Register (WDTLD) .............. 49 1.5.12 Real Time Clock .................................................................... 49 1.5.12.1 RTC Control Register (RTCCON) ................. 49 1.5.12.2 RTC Time Registers (TIME0-TIME3)............. 50 1.5.12.3 RTC Alarm Registers (ALM0-ALM3) ............. 51 1.5.13 CAS Tone and FSK Detector for CLI/CIDCW ....................... 53 1.5.13.1 CAS Tone Detector........................................ 53 1.5.13.2 FSK Detector ................................................. 53 1.5.13.3 FSK Demodulator.......................................... 54 1.5.13.4 Detect Control Register (CASDET)............... 54 1.5.13.5 FSK Buffer Register (FSKBUF)..................... 56 1.5.13.6 Example of Using the Detector for Off Hook operations 56 1.5.14 8051 Accumulator, Flags and Stack Pointer........................ 58 1.5.14.1 Accumulator Registers (A,B) ........................ 58 1.5.14.2 Program Status Word Register (PSW) ......... 58 1.5.14.3 Stack Point Register (SP) ............................ 59 1.5.15 Timers and Serial Port .......................................................... 60 1.5.15.1 Timer/Counter Control Register (TCON)..... 60 1.5.15.2 Timer/Counter Mode Register (TMOD)........ 61 1.5.15.3 Timer/Counter Registers (TL0 TL1 TH0 TH1)62 1.5.15.4 Serial Port Control Register (SCON) ........... 62 1.5.15.5 Serial Port Buffer Register (SBUF).............. 63 1.6 Modem General Description ............................................................. 64 1.6.1 Tx USART .............................................................................. 66 1.6.2 FSK and QAM/DPSK Modulators ......................................... 67 1.6.3 Tx Filter and Equaliser.......................................................... 68 1.6.4 DTMF/Tone Generator .......................................................... 68 1.6.5 Tx Level Control and Output Drivers ................................... 68 1.6.6 DTMF Decoder and Tone Detectors..................................... 69 1.6.7 Rx Modem Filterering and Demodulation............................ 70 1.6.8 Rx Modem Pattern Detectors and Descrambler .................. 71 1.6.9 Rx Data Register and USART ............................................... 71 1.6.10 Analogue Signal Routing...................................................... 73 1.6.11 'C-BUS' Interface ................................................................... 73 1.6.11.1 General Reset Command.............................. 73 1.6.11.2 General Control Register .............................. 74 1.6.11.3 Transmit Mode Register ............................... 76 1.6.11.4 Receive Mode Register ................................. 80 1.6.11.5 Tx Data Register............................................ 82 1.6.11.6 Rx Data Register............................................ 82 1.6.11.7 Analogue Signal Path Register .................... 82 1.6.11.8 Status Register.............................................. 84 1.6.11.9 Status Register.............................................. 87 1.6.11.10 Programming Register.................................. 88 1.6.11.11 Other Registers ............................................. 90
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1.7
Performance Specification................................................................ 91 1.7.1 Electrical Performance.......................................................... 91 1.7.1.1 Absolute Maximum Ratings ..................................... 91 1.7.1.2 Operating Limits ....................................................... 91 1.7.1.3 Operating Characteristics ........................................ 92 1.7.2 Packaging............................................................................ 103
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1.2
Block Diagram
Figure 1 Block Diagram
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1.3
Signal List
Signal Name VCAP MUXAD Type O/P I/P Decoupling capacitor Multiplexed address/data bus select for external memory. Tie to DVSS for non-multiplexed address/data. Tie to DVDD for multiplexed address/data (frees up the D7-0 pins for alternative functions). The input to the 11.0592MHz or 12.288MHz oscillator circuit from the Xtal or external clock source. The output of the on-chip 11.0592MHz/12.288MHz Xtal oscillator circuit. The digital negative supply rail (ground). The input to the 32.768kHz oscillator circuit from the Xtal. The output of the on-chip 32.768kHz Xtal oscillator circuit. Can also be used to output an internally derived 32.768kHz signal. The digital positive supply rail. Port 3 bit 0. Alternative function is serial port (RS232) receive data. Port 3 bit 1. Alternative function is serial port (RS232) transmit data. Port 3 bit 2. Alternative function is Int0 interrupt input. Port 3 bit 3. Alternative function is Int1 interrupt input. Port 3 bit 4. Alternative function is Timer 0 control input. Port 3 bit 5. Alternative function is Timer 1 control input. Port 3 bit 6. Alternative function is PWM 1 output. Port 3 bit 7. Alternative function is PWM 2 output. The digital negative supply rail (ground). Port 1 bits 7-0. Alternative function is keyboard row input pins, bits 7-0. Description
Package L8 Pin No. 1 2
3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
XTAL XTALN DVSS X32K X32KN DVDD P3.0 (RXD) P3.1 (TXD) P3.2 (INT0) P3.3 (INT1) P3.4 (T0) P3.5 (T1) P3.6 (PWM1) P3.7 (PWM2) DVSS P1.0 (KBR.0) P1.1 (KBR.1) P1.2 (KBR.2) P1.3 (KBR.3) P1.4 (KBR.4) P1.5 (KBR.5) P1.6 (KBR.6) P1.7 (KBR.7) DVDD P4.0 (KBC.0) P4.1 (KBC.1) P4.2 (KBC.2) P4.3 (KBC.3) P4.4 (KBC.4) P4.5 (KBC.5) P4.6 (KBC.6) P4.7 (KBC.7)
I/P O/P Power I/P O/P Power BI BI BI BI BI BI BI BI Power BI BI BI BI BI BI BI BI Power BI BI BI BI BI BI BI BI
The digital positive supply rail. Port 4 bits 7-0. Alternative function is keyboard column drivers, bits 7-0. Unused column drivers remain as general-purpose port pins.
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Package L8 35 36 37 38 39 40 41 42 43 44 45 46 47 48
Signal DVSS P5.0 (KBC.8) P5.1 (KBC.9) P5.2 (KBC.10) P5.3 (KBC.11) P5.4 (KBC.12) DVDD D0 : P5.5 (KBC.13) D1 : P5.6 (KBC.14) D2 : P5.7 (KBC.15) D3 : P0.0 D4 : P0.1 D5 : P0.2 D6 : INT9 Power BI BI BI BI BI Power BI : BI BI : BI BI : BI BI : BI BI : BI BI : BI BI : I/P
Description The digital negative supply rail (ground). Port 5 bits 4-0. Alternative function is keyboard column drivers, bits 12-8. Unused column drivers remain as general-purpose port pins.
The digital positive supply rail. With pin MUXAD tied to DVSS: Bi-directional data bus for external memory. With pin MUXAD tied to DVDD: Port 5 bits 7-5. Alternative function is keyboard column drivers, bits 15-13. Unused column drivers remain as general-purpose port pins. Port 0 bits 2-0.
Super priority interrupt (active low). When configured as an interrupt, this pin should be fitted with a 100k pullup resistor to DVDD (not shown in Figure 2a), if driven by an open-drain driver. Address latch enable. The digital negative supply rail (ground). With pin MUXAD tied to DVSS: With pin MUXAD tied to DVDD: External memory interface multiplexed address (LSB) and data. While ALE is high, the LSB of the memory address is driven out. When ALE goes low, the pins change to a bi-directional data bus. External memory interface address bus (LSB).
49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67
D7 : ALE DVSS A0 : AD0 A1 : AD1 A2 : AD2 A3 : AD3 A4 : AD4 A5 : AD5 A6 : AD6 A7 : AD7 DVDD A8 A9 A10 A11 A12 A13 A14 A15
BI : O/P Power O/P : BI O/P : BI O/P : BI O/P : BI O/P : BI O/P : BI O/P : BI O/P : BI Power O/P O/P O/P O/P O/P O/P O/P O/P The digital positive supply rail.
External memory interface address bus (MSB).
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Package L8 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89
Signal DVSS WEN OEN CSN1 CSN2 CSN3 RESETN VCAP AVDD VREF VINA VINB AVSS LINERXF LINERXBN LINERXN LINERXP PHONERXF PHONERXN PHONERXP AVSS VBIAS Power O/P O/P O/P O/P O/P I/P O/P Power O/P I/P I/P Power O/P I/P I/P I/P O/P I/P I/P Power O/P
Description The digital negative supply rail (ground). External memory read/~write control. External memory output enable (active low). External memory chip select #1 (active low). External memory chip select #2 (active low). External memory chip select #3 (active low). Chip reset (active low). Requires an external 100k pullup resistor to DVDD. Decoupling capacitor The analogue positive supply rail. Levels and thresholds within the modem are proportional to this voltage. A/D converter voltage reference output. A/D converter input A. This input should be carefully decoupled to AVSS to avoid instability in readings. A/D converter input B. This input should be carefully decoupled to AVSS to avoid instability in readings. The analogue negative supply rail (ground). The output of the Line Rx Input Amplifier. An auxiliary inverting input to the Line Rx Input Amplifier, switched in parallel with LINERXN to boost gain. The inverting input to the Line Rx Input Amplifier. The non-inverting input to the Line Rx Input Amplifier. The output of the Phone Rx Input Amplifier. The inverting input to the Phone Rx Input Amplifier. The non-inverting input to the Phone Rx Input Amplifier. The analogue negative supply rail (ground). Internally generated bias voltage of approximately AVSS/2, except when the device is in Powersave mode, when VBIAS will discharge to AVSS. Should be decoupled to AVSS by a capacitor mounted close to the device pins.
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Package L8 90 91 92 93 94 95
Signal PHONETXN PHONETXP LINETXN LINETXP AVDD HT O/P O/P O/P O/P Power BI
Description The inverted output of the Phone Tx Output Driver. The non-inverted output of the Phone Tx Output Driver. The inverted output of the Line Tx Output Driver. The non-inverted output of the Line Tx Output Driver. The analogue positive supply rail. Levels and thresholds within the modem are proportional to this voltage. Open drain output and Schmitt trigger input forming part of the Hook signal detector. Connect to DVDD if Hook Detector not used. Schmitt trigger input to the Hook signal detector. Connect to DVSS if Hook Detector not used. The digital negative supply rail (ground). Relay drive output, low resistance pull down to DVSS when active, medium resistance pull up to DVDD when inactive. Schmitt trigger input to the Ring signal detector. Connect to DVSS if Ring Detector not used. Open drain output and Schmitt trigger input forming part of the Ring signal detector. Connect to DVDD if Ring Detector not used.
96 97 98 99 100
HD DVSS RDRVN RD RT
I/P Power O/P I/P BI
Notes:
I/P O/P BI
= = =
Input Output Bi-directional
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1.4 External Components
Figure 2a Recommended External Components for a Typical Application C1, C4,C17 C5, C6, C7,C15,C16 C10, C11 (optional see note) C14 R1 (optional see note) X1 10F 100nF 18pF 1F 10M 11.0592MHz or 12.288MHz C2, C3, C12 C8, C9 C13 D1 R2 X2 (optional see note) 100nF 22pF 1nF 1N914 100k 32.768kHz
Resistors 5%, capacitors and inductors 20% unless otherwise stated. Note: The components C10, C11, R1 and X2 are optional, they are not required if the 32.768kHz clock is derived internally from the 11.0592MHz/12.288MHz system clock. See section 1.5.6 for details.
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The CMX850 modem and ADC interfaces are capable of detecting and decoding small amplitude signals. To achieve this, DVDD, AVDD and VBIAS should be decoupled and the receive path protected from extraneous in-band signals. It is recommended that the printed circuit board is laid out with AVSS and DVSS ground planes in the CMX850 area, as shown in Figure 2b, with provision to make a link between them close to the CMX850. To provide a low impedance connection to ground, the decoupling capacitors C1 - C7, C12, C13 and C15 - C17 must be mounted as close to the CMX850 as possible and connected directly to their respective ground plane. The use of surface mounted capacitors is recommended. VBIAS is used as an internal reference for detecting and generating the various analogue signals. It must be carefully decoupled, to ensure its integrity. Apart from the decoupling capacitor shown (C12), no other loads are allowed. If VBIAS needs to be used to set external analogue levels, it must be buffered with a high input impedance buffer. VREF is the internal reference voltage generated for the ADC. For best ADC performance, it is recommended that a 1nF capacitor be placed on this pin and connected to AVSS. The pin may also be used as a reference voltage externally (see section 1.5.8), however it is recommended that a maximum of 1A is drawn from the pin. If more current is required externally, then a suitable buffer must be used. The DVSS to the Xtal oscillator capacitors C8 - C11 should be of low impedance and preferably be part of the DVSS ground plane to ensure reliable start up. The resistor across the 32.768kHz Xtal should be 10M for best performance. Using a smaller resistor will result in increased power consumption.
DVSS Ground Plane AVSS Ground Plane
VCAP C15 C7 DVDD
DVSS
DVSS
DVSS
75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
L1 AVDD C2 C1 + AVDD VREF C13 AVSS
DVSS
DVSS AVSS AVSS AVSS AVSS VBIAS C3 AVSS AVDD C12 DVSS C6 C17+ DVSS DVSS
98
DVDD
DVSS Provision for a Wire Link
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25
DVDD
DVDD
VCAP
DVSS
DVSS
L2 DVDD C4 + DVSS
C16 C5
DVSS
DVSS
DVSS DVSS
DVSS
DVSS
Figure 2b Recommended Power Supply Connections and De-coupling
C1, C4, C17 C5, C6, C7, C15, C16 L1
10F 100nF 100nF 100nH (optional, see note)
C2, C3, C12 C13 L2
100nF 1nF 100nH (optional, see note)
Note: The inductors L1 and L2 can be omitted but this may degrade system performance.
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1.4.1
Ring Detector Interface
Figure 3 shows how the Modem may be used to detect the large amplitude ringing signal voltage present on the 2-wire line at the start of an incoming telephone call. The ring signal is usually applied at the subscriber's exchange as an ac voltage inserted in series with one of the telephone wires and will pass through either C20 and R20 or C21 and R21 to appear at the top end of R22 (point X in Figure 3) in a rectified and attenuated form. The signal at point X is further attenuated by the potential divider formed by R22 and R23 before being applied to the CMX850 RD input. If the amplitude of the signal appearing at RD is greater than the input threshold (Vthi) of Schmitt trigger 'A' then the N transistor connected to RT will be turned on, pulling the voltage at RT to DVSS by discharging the external capacitor C22. The output of the Schmitt trigger 'B' will then go high, setting bit 14 (Ring Detect) of the modem's Status Register 1. The minimum amplitude ringing signal that is certain to be detected is: ( 0.7 + Vthi x [R20 + R22 + R23] / R23 ) x 0.707 Vrms where Vthi is the high-going threshold voltage of the Schmitt trigger A. See Figure 16. With R20 - R22 all 470k as Figure 3, then setting R23 to 68k will guarantee detection of ringing signals of 40Vrms and above for DVDD over the range 3V to 3.6V.
C20 2-Wire Telephone Line C21
R20 X
DVSS
CMX850 B R22 R23 RD A
To Status Register
D1 - 4
R21
DVSS
C22
RT
R24
DVDD
Ring signal Bridge rectifier o/p (X) RT Status Register bit 14 (Ring Detect)
Vthi
DVSS
Vthi
DVSS
R20, 21, 22 R23 R24
470k See text 470k
C20, 21 C22 D1-4
0.1F 0.33F 1N4004
Resistors 5%, capacitors 20% Figure 3 Ring Signal Detector Interface Circuit
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If the time constant of R24 and C22 is large enough then the voltage on RT will remain below the threshold of the 'B' Schmitt trigger for the duration of a ring cycle. The time for the voltage on RT to charge from DVSS towards DVDD can be derived from the formula: VRT = DVDD x [1 - exp(-t/(R24 x C22)) ] As the Schmitt trigger high-going input threshold voltage (Vthi) has a minimum value of 0.56 x DVDD, then the Schmitt trigger B output will remain high for a time of at least 0.821 x R24 x C22 following a pulse at RD. The values of R24 and C22 given in Figure 3 (470k and 0.33F) give a minimum RT charge time of 100 ms, which is adequate for ring frequencies of 10Hz or above. Note that the circuit will also respond to a telephone line voltage reversal. If necessary the C can distinguish between a Ring signal and a line voltage reversal by measuring the time that bit 14 of the modem's Status Register 1 (Ring Detect) is high. If the Ring detect function is not used then pin RD should be connected to DVSS and RT to DVDD. 1.4.2 Hook Detector Interface
This is identical internally to the Ring Detector interface circuit and similar components could be used externally, with appropriate values, if hook detection is to be performed by detecting a voltage change across the tip and ring lines to the local phone.
1.4.3
RESETN pin
When this pin is taken low, it resets the CMX850, which includes the C and modem. The reset to the modem performs the same operation as a C-BUS General Reset command. As a consequence the modem will enter the powersaved state. Refer to section 1.6.11.1 (General Reset Command) and 1.6.11.2 (General Control Register, Powerup bit) for further information. At the same time as the modem is reset, the C and its SFRs will also be reset. No further accesses are made to external memory until the RESETN pin makes a low to high transition, when program execution will begin from either external memory or internal (local) BOOT ROM, depending on the duration of the RESETN pulse and the state of the VBIAS pin during the low to high transition of the RESETN pin. See section 1.4.4 for a more detailed description of local BOOT ROM execution. On initial power-up, the CMX850 performs a power-on reset which is similar to taking the RESETN pin low. The following SFR registers of the C are not affected by the RESETN pin or a power-up reset. The reason for not resetting these bits is so that i) the real time clock doesn't stop when RESETN is asserted, ii) the user can tell if the watchdog timed out and caused the reset, and iii) established practice is maintained - in the case of the standard 8051 SFRs. OBSCON b7..0: These are cleared by a power-up reset, but are not affected by the RESETN pin. WDTCON b2: This bit is cleared by a power-up reset, but is not affected by the RESETN pin. RTCCON b7 and b3: These bits are not affected by either power-up reset or RESETN; they are indeterminate on power-up.
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TIME0, 1, 2, 3 (all 32 bits): These bits are not affected by either power-up reset or RESETN; they are indeterminate on power-up. ALM0, 1, 2, 3 (all 32 bits): These bits are not affected by either power-up reset or RESETN; they are indeterminate on power-up. SBUF b7..0: A standard 8051 C register (UART data buffer). The bits of this register are not affected by either powerup reset or RESETN: they are indeterminate on power-up.
1.4.4
Local BOOT ROM
The CMX850 can be configured to execute the "thin stub" code, which resides in the on-chip BOOT ROM, instead of the normal program contained in the user's external ROM. This "thin stub" code will download a "thick stub" code from the serial port, place it in XRAM and execute it. The template for the "thick stub" code is supplied by CML to enable customers to create a "thick stub" for the purposes of reprogramming FLASH memory, which the user may fit in place of external ROM. An 11.0592 MHz xtal must be used to obtain the standard 19,200 baud rate, in order to reprogram FLASH memory from the 8051 C serial port. This baud rate is fixed by the "thin stub" code and the chip reset mechanism. It is not variable. Please contact CML Technical Support for details of suitable FLASH memories. To execute the BOOT ROM program: 1. Make sure the device is powered up. 2. Apply reset by pulling the RESETN pin low for a minimum of two seconds. 3. While reset is active, short the VBIAS pin to the analogue VDD supply. This can be done with a wire link or an active device (the voltage on the VBIAS pin must be no lower than VDD - 0.1V). Note that while reset is active, the VBIAS pin looks like a 50k (nominal) resistor to VSS in parallel with the off-chip decoupling capacitor. 4. Remove reset from the device by taking the RESETN pin high. The voltage on the VBIAS pin must be held for at least 1s. The device will then boot up from the internal BOOT ROM. 5. To get the device out of "BOOT ROM" mode it must be reset again with the connection between VBIAS and VDD removed (so that the voltage on the VBIAS pin is less than 1/2VDD). Alternatively, a reset pulse of less than 0.4 seconds will get the device out of "BOOT ROM" mode, whatever voltage is on the VBIAS pin. 1.4.5 Line Interface A line interface circuit is needed to provide dc isolation and to terminate the line. 2-Wire Line Interface Figure 4a shows an interface for use with a USA 600 2-wire line. The complex line termination is provided by R10, R13, C17, C18, C19 and C24, high frequency noise is attenuated by C23 and C24, while R11 and R12 set the receive signal level into the modem. R14 connects in parallel with R11 when enabled in the Analogue Signal Path Register. This is for the purpose of increasing gain, which is necessary to compensate for signal attenuation during on-hook CLI detection. Tx rejection into the Rx is provided by R15. For clarity, not all of the 2-wire line protection circuits have been shown. Components for use in other countries vary by country.
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R10 R11, 14 R12 R13 R15
180k See text 100k 600 120k
C17 C18 C19 C23 C24 Resistors 5%, capacitors 20%
100nF 47pF (USA) wire link (USA) 100pF 33nF
Figure 4a 2-Wire Line Interface Circuit The transmit line signal level is determined by the voltage swing between the TXP and TXN pins, less 6dB due to the line termination resistor R13, and less the loss in the line coupling transformer. Allowing for 1dB loss in the transformer, then with the Tx Mode Register set for a Tx Level Control gain of 0dB the nominal transmit line levels will be: VDD = 3.3V -9.2dBm -9.2dBm -5.2 and -7.2 dBm
QAM, DPSK and FSK Tx modes (no guard tone) Single tone transmit mode DTMF transmit mode
For a line impedance of 600, 0dBm = 775mVrms. See also section 1.7.1.3. In the receive direction, the signal detection thresholds within the modem are proportional to VDD and are affected by the Rx Gain Control gain setting in the Rx Mode Register. The signal level into the modem is affected by the line coupling transformer loss and the values of R11 and R12 of Figure 4a. Assuming 1dB transformer loss, the Rx Gain Control programmed to 0dB and R12 = 100k, then for correct operation (see section 1.7.1.3) the value of R11 should be equal to 500 / VDD k, i.e. 150k at VDD = 3.3V. 4-Wire Line Interface Figure 4b shows a simplified interface for use with a 600 4-wire line. The line terminations are provided by R13 and R16, high frequency noise is attenuated by C23 while R11 and R12 set the receive signal level into the modem. R14 connects in parallel with R11 when enabled in the Analogue Signal Path Register. This is for the purpose of increasing gain, which is necessary to compensate for signal attenuation during on-hook CLI detection.
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Transmit and receive line level settings and the value of R11 and R14 are as for the 2-wire circuit.
R13, 16 R11, 14 R12
600 See text 100k
C3 C19 C23 Resistors 5%, capacitors 20%
100nF 33nF 100pF
Figure 4b Simplified 4-Wire Line Interface Circuit
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D/850/6
Communications Controller
CMX850
1.5 Microcontroller Core
The CMX850 microcontroller core is software and cycle-timing compatible with the industry standard 80C51 and includes standard hardware such as a 256-byte local RAM, timer/counters, serial interface and interrupt controller. The microcontroller architecture is further enhanced by the addition of extra core functionality along with a comprehensive set of on-chip "peripheral" hardware. These are controlled by new registers mapped into the 8051's Special Function Register space. These additional features include: * * * * * * * * * * * * * * * Dual data pointers 8kbyte on-chip XRAM General-purpose ports (up to 35 pins) with explicit direction and open-drain control, and optional pull-up resistors External 64kbyte program address space, extendable using bank switching Four independently selectable XRAM source/destination areas, including on-chip XRAM and three off-chip areas accessible through separate chip select pins Optional "MOVX" wait state for slow external peripherals 8 extra interrupts Advanced oscillator and power saving controls C-BUS controller connected to on-chip DSP modem Keyboard encoder (up to 128 keys) Dual channel 10-bit ADC with threshold comparators and internal bandgap reference Real time clock and alarm Watchdog timer Dual pulse-width modulators Debugger support through the use of a super priority interrupt pin
This datasheet contains a detailed description of the features unique to the CMX850 device. For a more detailed description of the 8051 C architecture, instruction set, timers, serial port, interrupts and CPU timing, reference should be made to Programmers Guides, Hardware Descriptions and similar documentation on the 8051 C architecture, which is widely available. Please contact CML Technical Support in case of difficulty.
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D/850/6
Communications Controller
CMX850
1.5.1
Special Function Register Memory Map
The CMX850 microcontroller's special function register (SFR) area contains the complete set of standard 8051 SFRs, along with the additional SFRs required to control the CMX850's extra hardware functions.
Bit addressable (lsb ) $F8 $F0 $E8 $E0 $D8 $D0 $C8 $C0 $B8 $B0 $A8 $A0 $98 $90 $88 $80 '..... 000' (B) CASDET (ACC) P5 (PSW) P4 (IP) (P3) (IE) (P2) (SCON) (P1) (TCON) (P0) P5DIR FSKBUF P4DIR IP_1 P3DIR IE_1 (SBUF) P1DIR (TMOD) (SP) '..... 001' '..... 010' MEMCON WDTCON CBUSCON ADCCON1 P5OD '..... 011' RTCCON WDTLD CBUSBUF ADCCON2 P5RES Standard 80C51 SFRs are shown in parentheses '..... 100' TIME0 ALM0 KBCON ADCBUFL '..... 101' TIME1 ALM1 KBSTAT ADCBUFH PWMCON '..... 110' TIME2 ALM2 KBBUF ADCTHRL PWM1 '..... 111' TIME3 ALM3 ADCTHRH PWM2
P4OD P3OD ICON1A
P4RES P3RES ICON1B OSCCON P0DIR (TH0) DPL1 SPDCON (TH1) DPH1 SPXMASK PDXMASK TESTCON (PCON)
P1OD (TL0) (DPL)
P1RES (TL1) (DPH)
DPS
Table 1 Special Function Registers The CMX850's SFRs are mapped into the local RAM address space between locations $80 and $FF, and are accessible by standard 8051 instructions which use direct addressing. SFRs whose address is divisible by 8 are also accessible using bit-addressing instructions. The TESTCON SFR is used for production test only and should not be written to under any circumstances. Similarly, any undefined addresses in the table should not be written to, otherwise device operation may become unpredictable. 1.5.2 Dual Data Pointer
The standard 8051 C has a single 16-bit data pointer DPTR which can be used to address XRAM or program memory, using MOVX and MOVC instructions respectively. The DPTR register is also mapped into two 8-bit SFRs, DPL and DPH. The CMX850 has an additional 16-bit data pointer DPTR1 that can significantly speed up block moves by allowing 16-bit source and destination pointers to be maintained simultaneously. DPTR1 is mapped into SFR registers DPL1 and DPH1. A separate SFR register DPS is used to select between DPTR and DPTR1: all instructions that use the data pointer directly (INC DPTR; MOV DPTR,#data16; MOVC A,@A+DPTR; MOVX A,@DPTR; MOVX @DPTR,A) will be directed to whichever data pointer is currently selected by DPS. Swapping between the two data pointers can be easily achieved by using the increment instruction, INC, to toggle DPS bit 0. 1.5.2.1 DPTR Registers (DPL/DPH, DPL1/DPH1) DPL: SFR Address $82 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
DPTR Low Byte
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Communications Controller
CMX850
DPH: SFR Address $83 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
DPTR High Byte
DPL1: SFR Address $84 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
DPTR1 Low Byte
DPH1: SFR Address $85 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
DPTR1 High Byte
1.5.2.2 Data Pointer Select Register (DPS) DPS: SFR Address $86 Bit b0 is cleared to 0 on reset. Other bits are unused, and are 0. Bit:
7 6 5 4 3 2 1 0 Data pointer select
Unused (always read as 0)
DPS Register b0: Set to 0 to select DPTR, set to 1 to select DPTR1
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D/850/6
Communications Controller
CMX850
1.5.3
I/O Ports
The 8051 C port structure within the CMX850 has been enhanced by the addition of two extra byte-wide ports, port 4 and port 5. The ports have also been enhanced for low power operation by the addition of explicit port direction control registers, which means that port input pins consume no dc current when driven with a logic 0 (standard 8051 port inputs consume several tens of microamps of dc current per pin when driven with a logic 0). To further enhance flexibility, all of the port 1, 3, 4 and 5 pins can be individually configured as open-drain output drivers, and with optional pull-up resistors. The port configuration within the CMX850 is shown in Table 2. Note that, in order for port bit P3.1 (TXD) to be used to output serial port data or clock pulses in mode 0-3, both the P3 output latch bit 1 and the P3DIR direction latch bit 1 must be loaded with a logic 1. Similarly, in order for port bit P3.0 (RXD) to be used to output serial port data in mode 0, both the P3 output latch bit 0 and the P3DIR direction latch bit 0 must be loaded with a logic 1. Port Port 0 Function When the CMX850 is configured with a multiplexed external memory interface (pin MUXAD = 1), port 0 bits 2-0 are available as I/O pins. The remaining port 0 bits (73) are unused. Note that the port 0 pins do not have memory address/data driven onto them during an external memory access, as would happen on a standard 8051: the CMX850 external memory interface is completely separate from the port 0 circuit. Port 1 bits 7-0 are available as I/O pins. They are automatically configured as keyboard row input pins with pull-up resistors when the keyboard encoder is enabled. Port 2 bits 7-0 are not available directly as I/O pins, but the contents of the bytewide port 2 output latch is used during MOVX A,@Ri and MOVX @Ri,A instructions to form the upper eight address bits on pins A15-8. This is done to maintain compatibility with the standard 8051 C instruction set. Port 3 bits 7-0 are available as I/O pins. Each pin also has an alternative output function, as shown below. Pins P3.6 and P3.7 are automatically configured as an output when the associated PWM block is enabled. The other alternative pin functions require the correct pin direction to be explicitly configured using the P3DIR register. Alternative function Port RXD (Serial port receive data) P3.0 TXD (Serial port transmit data) P3.1 Int0 (External interrupt 0) P3.2 Int1 (External interrupt 1) P3.3 T0 (Timer/counter 0 external input) P3.4 T1 (Timer/counter 1 external input) P3.5 PWM1 (Pulse-width modulator 1 output) P3.6 P3.7 PWM2 (Pulse-width modulator 2 output) Port 4 bits 7-0 are available as I/O pins. Between one and eight port 4 pins are automatically configured as open-drain column drivers when the keyboard encoder is enabled, depending on the contents of the KBCON register. Port 5 bits 7-0 are available as I/O pins (bits 7-5 are only available if the CMX850 is configured with a multiplexed external memory interface). Up to eight port 5 pins are automatically configured as open-drain column drivers when the keyboard encoder is enabled, depending on the contents of the KBCON register. Table 2 I/O Port Function
Port 1
Port 2
Port 3
Port 4
Port 5
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D/850/6
Communications Controller
CMX850
1.5.3.1 Port Data Registers (P0-P5) The 8051 C retains the standard port registers (P0, P1, P2, P3) as well as having two new ports, P4 and P5. Writing to these port SFRs loads the associated output data register, which gets driven onto those device pins that are configured as outputs. Reading from a port SFR will either read the contents of the port output data register, or read directly from the port pins, depending on which instruction is used. The instructions that read the data register rather than the pins are those that perform a read-modify-write operation on a port or a port bit (this is explained in more detail in any standard 8051 C documentation). P0: SFR Address $80 P1: SFR Address $90 P2: SFR Address $A0 P3: SFR Address $B0 P4: SFR Address $C0 P5: SFR Address $D8 All bits set to 1 on reset. These registers are bit addressable. Bit:
7 6 5 4 3 2 1 0
Bits 7-0 of the port data registers
1.5.3.2 Port Direction Registers (P0DIR-P5DIR) Ports 0, 1, 3, 4 and 5 each have a direction control register that allows individual port pins to be configured either as an input or an output. The bits should be cleared to a 0 for an input, or set to 1 for an output. P0DIR: SFR Address $94 P1DIR: SFR Address $91 P3DIR: SFR Address $B1 P4DIR: SFR Address $C1 P5DIR: SFR Address $D9 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Bits 7-0 of the direction control register
1.5.3.3 Port Open-Drain Registers (P1OD-P5OD) Ports 1, 3, 4 and 5 each have an open-drain control register which allows individual port outputs to be configured either with a pull-up/pull-down driver or with an open-drain driver. The bits should be cleared to a 0 for an active pull-up/pull-down driver, or set to 1 for an open-drain driver. Note that if a pin is configured as an input by the port direction control register, then the pin driver will go into a high impedance state irrespective of the contents of the associated open-drain control register bit. P1OD: SFR Address $92 P3OD: SFR Address $B2 P4OD: SFR Address $C2 P5OD: SFR Address $DA All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Bits 7-0 of the open-drain control register
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D/850/6
Communications Controller
CMX850
1.5.3.4 Port Res Pull-up Registers (P1RES-P5RES) Ports 1, 3, 4 and 5 each have a resistor pull-up control register which allows individual port pins to be configured either with or without a pull-up resistor. The bits should be cleared to a 0 if no resistor is required, or set to 1 to connect a 50k (nominal) resistor between the pin and DVDD. A port pin should not be configured with a pull-up resistor at the same time as being configured as an output with active pull-up/pulldown drivers, otherwise power will be needlessly wasted when driving out a logic 0. P1RES: SFR Address $93 P3RES: SFR Address $B3 P4RES: SFR Address $C3 P5RES: SFR Address $DB All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Bits 7-0 of the resistor pull-up control register
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D/850/6
Communications Controller
CMX850
1.5.4
Memory Interface
In addition to 256 bytes of scratchpad RAM, the CMX850 has 8kbytes of on-chip extension RAM (XRAM) and three separate 64k areas for off-chip memory and peripherals, accessible without glue logic via chip select pins CSN1, CSN2 and CSN3. External memory size can easily be increased to several megabytes by using a code-banking compiler along with a number of CMX850 port output pins as bank select bits. The CSN1 pin is normally used during program instruction fetches, although there is an option to replace the bottom 8kbytes of off-chip program ROM with the on-chip XRAM, allowing short sections of temporary program code to be executed from the on-chip XRAM. This could be used, for instance, when the CMX850 is re-programming external FLASH memory. MOVX read and write instructions can be independently directed to either the on-chip XRAM or any of the three off-chip memory areas, including the program ROM area (this allows the CMX850 to re-program external FLASH memory, if necessary). Combined with the dual data pointer architecture of the CMX850 microcontroller, this allows rapid block moves between any of the memory areas. The MOVX read and write instructions can also be independently stretched to allow access to slow memory or peripherals, without any external circuitry being required. All off-chip accesses use the same 16-bit address bus and 8-bit data bus, along with output enable (OEN) and write enable (WEN) control pins. The address and data pins can be configured to be non-multiplexed by tying input pin MUXAD low (address output on pins A15-0, bi-directional data uses pins D7-0), or the data can be multiplexed with the lower eight address pins (A7-0) by tying input pin MUXAD high. If configured with a multiplexed address/data bus, an external address latch (`373 or '573 type) is required. Pin D7 becomes an address latch enable (ALE), and pins D6-0 are reassigned as an extra interrupt pin and general-purpose port bits. During the time when ALE is high, the least significant byte (LSB) of the 16-bit memory address is driven onto pins A7-0. When ALE goes low, the LSB of the memory address gets held in the external address latch, and the A7-0 pins change to a bi-directional data bus. In order to minimise power consumption and EMI, the CMX850 only performs program memory reads when necessary, rather than doing continuous reads and discarding the unnecessary ones as on a standard 8051. This typically reduces the number of program read operations by 30% - 40%. Furthermore, when using a multiplexed address/data bus, unnecessary ALE pulses are inhibited. The CMX850 data pins (D7-0 for non-multiplexed, or A7-0 for multiplexed) can be configured with weak bus-holding devices to prevent voltage drift on the pins during long periods of inactivity (e.g. when in idle/power down mode, or executing programs from entirely within on-chip XRAM). This can help reduce unnecessary current consumption in devices connected to the data bus. The memory interface is configured using the MEMCON SFR. 1.5.4.1 Memory Control Register (MEMCON) MEMCON: SFR Address $FA All bits cleared to 0 on reset. Bit:
7 Enable bus-hold 6 Internal progam 5 MOVX write stretch 4 3 2 MOVX read stretch 1 0
MOVX write destination
MOVX read source
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D/850/6
Communications Controller
CMX850
MEMCON Register b7: Enable bus-hold b7 = 1 b7= 0 Enable data pin bus-holding devices Disable data pin bus-holding devices
MEMCON Register b6: Internal program b6 = 1 b6 = 0 On-chip XRAM mapped into bottom 8Kbytes of program memory Program memory is entirely off-chip
Allows temporary program code to be executed from on-chip XRAM. Note that any interrupt service routine vectors being used (these begin at locations $03 to $6B) should be duplicated in XRAM before setting this bit; alternatively the interrupts should be disabled. When MEMCON bit 6 is altered, even though the instruction that modifies it executes in the normal amount of time, there is an internal delay of 2 machine cycles before the switch between ROM and XRAM takes effect. MEMCON bit 6 can be changed without any problems when program execution is taking place in external ROM at an address of $2000 or above. Changing MEMCON bit 6 when program execution is taking place in external ROM or internal XRAM at an address between $0000 and $1FFF requires some care to prevent disruption of the desired program flow. MEMCON Register b5: MOVX write stretch b5 = 1 b5 = 0 MOVX write operations are stretched by one machine cycle (12 xtal cycles) MOVX write operations are not stretched
MEMCON Register b4-3: MOVX write destination b4 0 0 1 1 b3 0 1 0 1
MOVX write destination is on-chip XRAM MOVX write destination is off-chip, using pin CSN1 MOVX write destination is off-chip, using pin CSN2 MOVX write destination is off-chip, using pin CSN3
MEMCON Register b2: MOVX read stretch b2 = 1 b2 = 0 MOVX read operations are stretched by one machine cycle (12 xtal cycles) MOVX read operations are not stretched
MEMCON Register b1-0: MOVX read source b1 0 0 1 1 b0 0 1 0 1
MOVX read source is on-chip XRAM MOVX read source is off-chip, using pin CSN1 MOVX read source is off-chip, using pin CSN2 MOVX read source is off-chip, using pin CSN3
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D/850/6
Communications Controller
CMX850
1.5.5
Interrupts
The 8051 C interrupt logic has been extended, so that the original five interrupt sources (Int0, Timer0, Int1, Timer1, Serial) have been supplemented by eight new interrupt sources (Int2, Int3, Int4, Int5, Int6, Int7, Int8 and Int9). With the exception of Int9, these new interrupts are connected to the 8051 C's on-chip peripheral hardware logic as shown in Table 3, so that the hardware can be interrupt driven. Int9 is a super priority interrupt, which can interrupt both low and high priority interrupts, and is available on a device pin when the CMX850 is configured with a multiplexed memory address/data bus. This pin may be driven by an external ROM emulator to assist with program debugging. Interrupt signal Int2 (Int0) Int3 (Timer0) Int4 (Int1) Int5 (Timer1) Int6 (Serial) Int7 Int8 Int9 Hardware source CAS Detect Interrupt 0 input pin (P3.2) DSP Modem 8051 timer 0 Keyboard encoder Interrupt 1 input pin (P3.3) A/D converter 8051 timer 1 RTC time interrupt RI or TI from 8051 serial port RTC alarm interrupt Watchdog timeout Interrupt 9 input pin (D6)* Vector address $33 $03 $3B $0B $43 $13 $4B $1B $53 $23 $5B $63 $6B Priority within level 1 (Highest) 2 3 4 5 6 7 8 9 10 11 12 (Lowest) N/A (super priority)
* Note: D6 is only available as an interrupt with a multiplexed memory interface (pin MUXAD = 1) Table 3 Interrupt structure The "priority within level" structure is only used to resolve simultaneous interrupt requests of the same priority level. A low priority interrupt which is active cannot be interrupted by another low priority interrupt, but can be interrupted by a high priority interrupt or a super priority interrupt (Int9). A high priority interrupt which is active can only be interrupted by Int9. The new interrupts operate in a similar way to the existing Int0 and Int1 interrupts. Two new SFRs (IE_1 and IP_1) allow the interrupts to be individually enabled and have their priority set, and new SFRs ICON1A and ICON1B allow the interrupts to be configured as falling-edge or low-level triggered. In particular, the existing global interrupt enable bit (IE register bit 7) can be used to disable all of the new interrupts with the exception of Int9. It is recommended that the interrupts connected to the on-chip peripheral hardware (i.e. Int2 ... Int8) be configured as low-level triggered, with the application software explicitly clearing the interrupts by using the relevant mechanism built into each hardware block. Note that pin D6 does not have an on-chip pull-up resistor, so if this pin is used as a super priority interrupt (Int9) and is driven from a device with an open-drain output driver, an external pull-up resistor will need to be added. Further information about the Serial Port transmit/receive interrupt flags and the Int1-0 interrupt type control and edge flags can be found in the description of the SCON and TCON registers.
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D/850/6
Communications Controller
CMX850
1.5.5.1 Interrupt Enable Registers (IE, IE_1) IE: SFR Address $A8 Bits b7 and b4-0 cleared to 0 on reset. Bits b6-5 unused. This register is bit addressable. Bit:
7 Global Interrupt enable (EA) 6 Unused (set to 0) 5 Unused (set to 0) 4 Serial port interrupt enable (ES) 3 Timer 1 interrupt enable (ET1) 2 Int1 (P3.3) interrupt enable (EX1) 1 Timer 0 interrupt enable (ET0) 0 Int0 (P3.2) interrupt enable (EX0)
IE bits 4-0 can be used to individually enable each of the five standard 8051 interrupts: setting a bit to 1 enables the interrupt, clearing the bit to 0 disables the interrupt. Furthermore, all CMX850 interrupts with the exception of Int9 (i.e. Serial, Timer 1-0, Int 8-0) can be globally disabled by writing 0 to register IE bit 7 (EA). IE_1: SFR Address $A9 Bits b7-0 cleared to 0 on reset. Bit:
7 Int9 (pin D6) interrupt enable 6 Int8 interrupt enable Watchdog 5 Int7 interrupt enable RTC alarm 4 Int6 interrupt enable RTC time 3 Int5 interrupt enable ADC 2 Int4 interrupt enable Keyboard 1 Int3 interrupt enable C-BUS 0 Int2 interrupt enable CAS Det.
IE_1 bits 7-0 can be used to individually enable each of the eight new interrupts on the CMX850: setting a bit to 1 enables the interrupt, clearing the bit to 0 disables the interrupt. 1.5.5.2 Interrupt Priority Registers (IP, IP_1) IP: SFR Address $B8 Bits b4-0 cleared to 0 on reset. Bits b7-5 unused. This register is bit addressable. Bit:
7 Unused (set to 0) 6 Unused (set to 0) 5 Unused (set to 0) 4 Serial port interrupt priority (PS) 3 Timer 1 interrupt priority (PT1) 2 Int1 interrupt priority (PX1) 1 Timer 0 interrupt priority (PT0) 0 Int0 interrupt priority (PX0)
IP bits 4-0 can be used to set the priority level of the Serial Port, Timer1, Timer0, Int1 and Int0 interrupts: setting a bit to 1 configures the interrupt as high priority, clearing the bit to 0 configures the interrupt as low priority.
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D/850/6
Communications Controller
CMX850
IP_1: SFR Address $B9 Bits b6-0 cleared to 0 on reset. Bit b7 unused. Bit:
7 Unused (set to 0) 6 Int8 interrupt priority Watchdog 5 Int7 interrupt priority RTC alarm 4 Int6 interrupt priority RTC time 3 Int5 interrupt priority ADC 2 Int4 interrupt priority Keyboard 1 Int3 interrupt priority C-BUS 0 Int2 interrupt priority CAS Det.
IP_1 bits 6-0 can be used to set the priority level of interrupts Int8-2: setting a bit to 1 configures the interrupt as high priority, clearing the bit to 0 configures the interrupt as low priority. The Int9 interrupt is permanently configured with a super high priority, enabling it to interrupt any other currently active low or high priority interrupt. 1.5.5.3 Interrupt Control Registers (ICON1A/B) Each of the new interrupt inputs in the 8051 C has two associated control/status bits, residing in registers ICON1A and ICON1B. These operate in an identical way to the existing Int0 and Int1 control and status bits in the TCON register. Type control: these bits are set to 1 or cleared to 0 by software to configure the interrupts as falling-edge or low-level triggered respectively. It is recommended that the type control bits for Int8-2 be cleared to 0, i.e. configured as low-level triggered. Edge flag: when the interrupt is configured as falling-edge triggered, these bits are set to 1 by hardware to indicate that an edge has been detected, i.e. successive samples of the interrupt pin show a high in one machine cycle and a low in the next cycle, and will be cleared automatically when the service routine is called. When configured as low-level triggered interrupts, the edge flag will be updated once per cycle to reflect the state of the associated interrupt signal; the flag gets set to 1 if the interrupt line is active (i.e. low), and gets cleared to 0 if the interrupt line is inactive (high). ICON1A: SFR Address $AA All bits cleared to 0 on reset. Bit:
7 Int5 edge flag 6 Int5 type control 5 Int4 edge flag 4 Int4 type control 3 Int3 edge flag 2 Int3 type control 1 Int2 edge flag 0 Int2 type control
ICON1B: SFR Address $AB All bits cleared to 0 on reset. Bit:
7 Int9 edge flag 6 Int9 type control 5 Int8 edge flag 4 Int8 type control 3 Int7 edge flag 2 Int7 type control 1 Int6 edge flag 0 Int6 type control
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D/850/6
Communications Controller
CMX850
1.5.6
Oscillator and Power Management
Each main block of "peripheral" hardware surrounding the 8051 C core (Modem, CAS detector, A/D converter, PWM, RTC, WDT, Keyboard encoder) can be individually power saved through their associated control register, as shown in the table below: Function: Oscillator Control - 11.0592/12.288 MHz - 32 kHz - oscillator 8051 C Core - powersave/active - idle mode Auxiliary ADC 5.5 MHz RC Controlled by: OSCCON (9C) bits 4 and 5 OSCCON (9C) bit 1 OSCCON (9C) bits 4 and 5 PCON (87) bit 1 PCON (87) bit 2 ADCCON1 (E2) bit 2 and ADCCON2 (E3) bits 1, 2 and 3 CASDET (E9) bit 7 Needs System Clock to be active (9C bit 5) Comment:
CAS and FSK Detect
Automatically powers up VBIAS and Line Input Amplifier in the Modem. Also needs System Clock to be active (9C bit 5)
Keyboard Encoder PWM Outputs Real Time Clock (RTC) Watchdog Timer (WDT)
KBCON (EC) bits 6 and 7 PWMCON (DD) bits 6 and 7 RTCCON (FB) bit 7 WDTCON (F2) bit 7 Needs System Clock to be active (9C bit 5) excludes 32 kHz oscillator excludes 32 kHz oscillator
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CMX850
Function: Modem Core: - powersave/active
Controlled by: CBUS $E0 bit 8
Comment: addressed through: CBUSBUF (EB) bits 0 - 7 and CBUSCON (EA) bits 0 and 2
- idle mode - CBUS interface - modem functions - output amplifiers
CBUS $E0 bit 7 Always active CBUS $E0 bit 8 CBUS $E0 bit 8 and CBUS $EC bits 1 - 4 CBUS $E0 bit 8 CBUS $E0 bit 8 Always active Needs System Clock to be active (9C bit 5)
- input amplifiers - VBIAS generator - RD, HD and RDRVN
Table 4 Powersave Functions The CMX850 provides additional power management features, such as a low power RC oscillator and speed-control options for the 8051 clock, which allow the current consumption to be further reduced when the device is not fully operational (the standard 8051 Idle and Power Down modes of operation are also available). Further enhancements enable the 8051 C to automatically exit from speed control or power down modes, without requiring a system reset.
X32K Xtal Osc 32.768kHz X32KN
b2
32.768kHz clock
b0
XTAL Xtal Osc 11.0592MHz/ 12.288MHz RC Osc
OSCCON
b4
b4-3
32.768kHz Clock Divider
System clock
8051 Clock Divider
8051 clock
Exit Pdown SPDCON
SPXMASK
PDXMASK Int 8-2,0
Figure 5 Oscillator and Power Management
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D/850/6
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CMX850
1.5.6.1 Oscillator Control Register (OSCCON) The OSCCON register allows the selection of the main system clock (external Xtal or low power 5.5MHz RC oscillator), the 32.768kHz reference (external Xtal or system clock sub-division), and whether the clocks are power-saved when the 8051 C is in power down mode. OSCCON: SFR Address $9C All bits cleared to 0 when the device powers up. This register is not affected by the reset pin or a watchdog reset. Bit:
7 Generalpurpose flag 1 6 Generalpurpose flag 0 5 System clock power down 4 System clock source select 3 System Xtal freq. select 2 32.768k clock output enable 1 32.768k clock power down 0 32.768k clock source select
OSCCON Register b7-6: General-purpose flags 1-0 These bits are available for use as general-purpose flags; they do not affect the operation of the CMX850 hardware. Because these bits are cleared to 0 at power up but are not affected by the reset signal, a particular use for one of them is as a "cold-start" indicator: software would initially examine the flag to see if it contains a 0, and if so run a power-up initialisation routine before setting the flag to 1. If the CMX850 is subsequently reset the flag would read back as a 1, allowing the software to take alternative action (e.g. checking for a watchdog timeout). OSCCON Register b5: System clock power down Controls whether the system clock (either the RC or Xtal oscillator) is power saved when the 8051 C is in power down mode (power down mode is enabled by writing 1 to PCON bit 1). This depends on whether any of the peripheral blocks that use the system clock (i.e. Modem, CAS detector, A/D converter, PWM) need to remain active during 8051 power down. b5 = 1 b5 = 0 System clock remains active during 8051 power down System clock power saved during 8051 power down
OSCCON Register b4: System clock source select Controls whether the system clock is derived from the on-chip RC oscillator or from an external Xtal reference. The RC oscillator has a nominal frequency of 5.5MHz but consumes much less power than the Xtal oscillator, and so can be used when performing background tasks. The frequency of the RC oscillator is not sufficiently accurate to allow data transfers through the modem or serial port, however. The CMX850 powers up with the RC oscillator selected. When switching from the RC oscillator to the Xtal reference, there will be a delay while the Xtal oscillations build up (typically between 5ms and 20ms). In addition to this delay, the CMX850 waits 16 for 2 Xtal clock cycles to occur (~5ms - 6ms) during which time the system clock remains inactive. This ensures that the Xtal oscillations have been adequately established before proceeding. Note that the delay when switching back from the Xtal reference to the RC oscillator is typically less than 1s. b4 = 1 b4 = 0 System clock source is external Xtal, RC oscillator is powered down System clock source is 5.5MHz RC oscillator, external Xtal is powered down
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D/850/6
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CMX850
OSCCON Register b3: System crystal frequency select This bit should be set according to the system Xtal frequency being used. It is used to select the division ratio when the 32.768kHz reference is being derived from the main system clock (see description of OSCCON bit 0), and is also used to configure the DSP modem's clock dividers. This bit must be set to the correct state before the modem is used. b3 = 1 b3 = 0 System Xtal frequency is 11.0592MHz System Xtal frequency is 12.288MHz
OSCCON Register b2: 32.768kHz clock output enable This bit can be used to drive the 32.768kHz reference signal onto the X32KN pin for use by external circuitry. This can only be done if the 32.768kHz signal is derived from the main system clock; the function is disabled if using an external 32.768kHz Xtal reference (see description of OSCCON bit 0). b2 = 1 b2 = 0 Drive internal 32.768kHz reference onto X32KN pin (only if OSCCON bit 0 = 0) Do not drive internal 32.768kHz reference onto X32KN pin
OSCCON Register b1: 32.768kHz clock power down Controls whether the 32.768kHz clock is power saved when the 8051 C is in power down mode (power down mode is enabled by writing 1 to PCON bit 1). This depends on whether any of the peripheral blocks that use the 32.768kHz clock (i.e. RTC, WDT, Keyboard encoder) need to remain active during 8051 power down. b1 = 1 b1 = 0 32.768kHz clock remains active during 8051 power down 32.768kHz clock power saved during 8051 power down
OSCCON Register b0: 32.768kHz clock source select Controls whether the 32.768kHz clock is derived from a divided down main system clock (thus saving the expense of an external 32.768kHz Xtal), or uses the external Xtal (which allows the 32.768kHz clock to remain active while the system clock is powered down). If dividing down from the main system clock, the division ratio depends on whether an 11.0592MHz or 12.288MHz Xtal is used (see OSCCON bit 3), or whether the RC oscillator is selected. The accuracy of the 32.768kHz clock will only be as good as that of the selected reference source, which in the case of the RC oscillator is not good enough to maintain the correct time and date in the RTC. b0 = 1 b0 = 0 32.768kHz clock source is external Xtal 32.768kHz clock derived from main system clock: OSCCON b4 - 3 System clock division ratio (Due to odd division ratios, derived clock edge 0 X 1683/4 will jitter slightly but frequency will be accurate) 1 0 375 1 1 3371/2
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1.5.6.2 Speed Control Register (SPDCON) The 8051 C can be configured to run at a reduced internal clock speed, selectable through the SPDCON register, to allow software to continue executing but with substantially reduced power consumption. This is especially useful when combined with the low power RC oscillator option. Note that the 8051 C clock speed reduction does not alter the speed of the system clock used by the modem, A/D converter, or PWM blocks, but these blocks can be separately power saved if necessary. Running the C with a reduced clock speed will have a direct effect on the operation of the 8051 core's interrupt latency, serial port, and timers. The 8051 C clock can be selected to be a simple binary division of the main system clock, with division ratios selectable between /4 and /1024. However, because many external memory devices only enter low power standby mode when they are not being accessed, this simple binary division may not achieve the ultimate power saving possible. This is because the average time that the external memory is being accessed will not reduce. The 8051 C speed control mechanism can therefore be configured into a new "burst mode", where the C executes single complete instructions at a time at full speed, followed by longer periods of inactivity where the clock to the C is halted and external memory is held in standby (CSN1/2/3 and OEN pins held high). The average instruction throughput in burst mode is identical to that in non-burst mode, but the average time for which the external memory is active is greatly reduced. When in reduced speed mode or power down mode, the external data bus may float for considerable periods of time. This may cause unnecessary power consumption in devices connected to the data bus due to voltage drift on the bus pins. To avoid this, the memory interface can be configured with weak busholding devices to prevent this voltage drift (see description of MEMCON register). The 8051 C can be configured, using the SPXMASK register, to exit reduced speed mode automatically upon receiving an interrupt signal. This immediately causes the 8051 C to begin clocking again at full speed. SPDCON: SFR Address $9D All bits cleared to 0 on reset, or upon automatic exit of reduced speed operation. Bit:
7 6 5 4 3 Burst mode 2 1 0
Unused, always read as 0
8051 C clock speed select
SPDCON Register b7-4: Unused SPDCON Register b3: Burst mode b3 = 1 b3 = 0 Burst mode enabled Burst mode disabled
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SPDCON Register b7-4: 8051 C clock speed select b2 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1
8051 speed reduction disabled 8051 clock speed = divide by 4 8051 clock speed = divide by 16 8051 clock speed = divide by 64 8051 clock speed = divide by 256 8051 clock speed = divide by 1024 Reserved (do not use) Reserved (do not use)
1.5.6.3 Speed Control Exit Register (SPXMASK) This register can be configured to allow the 8051 C to be brought immediately out of speed control mode when any interrupt input line to the C (chosen from Int8-2 and Int0) goes active, i.e. low. To enable an interrupt to bring the 8051 C out of speed control mode, its associated mask bit in the SPXMASK register must be set to a 1, otherwise it should be cleared to 0. Note that the C can be brought out of speed control mode by an interrupt that is not enabled in the IE or IE_1 SFRs. This allows the speed control exit feature to be used even in systems that poll the peripheral hardware rather than have it interrupt driven. When an interrupt goes active whose mask bit is set to 1, the SPDCON register bits are all immediately cleared to 0. SPXMASK: SFR Address $9E All bits cleared to 0 on reset. Bit:
7 Int8 exit mask 6 Int7 exit mask 5 Int6 exit mask 4 Int5 exit mask 3 Int4 exit mask 2 Int3 exit mask 1 Int2 exit mask 0 Int0 exit mask
1.5.6.4 Power Down Exit Register (PDXMASK) This register can be configured to allow the 8051 C to be brought immediately out of power down mode when any interrupt input line to the C (chosen from Int8-2 and Int0) goes active, i.e. low. To enable an interrupt to bring the 8051 C out of power down mode, its associated mask bit in the PDXMASK register must be set to a 1, otherwise it should be cleared to 0. Note that the C can be brought out of power down mode by an interrupt that is not enabled in the IE or IE_1 SFRs. This allows the power down exit feature to be used even in systems that poll the peripheral hardware rather than have it interrupt driven. When the 8051 C is brought out of power down mode, register PCON bit 1 immediately gets cleared to 0 and the C will then respond to any active, enabled interrupts. If no enabled interrupt is active, the C will continue program execution from the instruction following the one that put it into power down mode. Note that if the CMX850 system clock source is configured as an external Xtal that gets disabled in power down mode (see OSCCON register), it will take a number of milliseconds for the Xtal to start up again and stabilise before the system begins clocking. If a more rapid response during a power down exit is required, either the Xtal should remain running during power down or the system clock source should be configured to be the RC oscillator before power down mode is entered.
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PDXMASK: SFR Address $9F All bits cleared to 0 on reset. Bit:
7 Int8 exit mask 6 Int7 exit mask 5 Int6 exit mask 4 Int5 exit mask 3 Int4 exit mask 2 Int3 exit mask 1 Int2 exit mask 0 Int0 exit mask
1.5.6.5 Power Control Register (PCON) PCON: SFR Address $87 Bits b7 and b3-0 cleared to 0 on reset. Bits b6-4 unused. Bit:
7 Double baud rate (SMOD) 6 Unused (set to 0) 5 Unused (set to 0) 4 Unused (set to 0) 3 General purpose flag (GF1) 2 General purpose flag (GF0) 1 Power Down bit (PD) 0 Idle Mode bit (IDL)
PCON Register b7: Double baud rate (SMOD) If Timer 1 is used to generate the serial port baud rate and SMOD = 1, the baud rate is doubled when the serial port is used in modes 1, 2 or 3. PCON Register b6-4: Unused PCON Register b3-2: General purpose flags (GF1, GF0) PCON Register b1: Power Down bit (PD) Setting this bit activates Power Down operation in the 8051 C (all activity within the 8051 CPU core and interrupt/serial port/timer logic is halted). It is possible to exit Power Down (i.e. clear PCON bit 1) by applying a hardware reset to the CMX850, or by activating an interrupt which has its associated mask bit in the PDXMASK register set (whether the interrupt is enabled or not). PCON Register b0: Idle Mode bit (IDL) Setting this bit activates Idle Mode operation in the 8051 C (activity within the 8051 CPU core is halted, but the interrupt/serial port/timer logic remains active). It is possible to exit Idle Mode (i.e. clear PCON bit 0) by applying a hardware reset to the CMX850, or by activating an enabled interrupt. If Power Down and Idle Mode are activated simultaneously, Power Down takes precedence.
1.5.7
Pulse Width Modulators
The CMX850 has two independent 8-bit Pulse Width Modulator (PWM) circuits, each with its own PWM data register (SFRs PWM1 and PWM2) and enable bit in the PWMCON SFR. When enabled, the PWM output is automatically driven onto the relevant device pin (the PWM 1 output is driven onto pin P3.6, the PWM 2 output is driven onto pin P3.7). This is done without altering the 8051's port control SFRs. Disabling a PWM causes its output pin to immediately revert to a general-purpose port function. The output of each PWM block is a fixed frequency square wave with a duty cycle controlled by the contents of the PWM1 or PWM2 SFR. The square wave frequency is 1/255 of the main system clock, i.e. approximately 43.4kHz if using an 11.0592MHz crystal, 48.2kHz if using a 12.288 MHz crystal, or 21.6kHz (nominal) if using the on-chip RC oscillator. The PWM output duty cycle is equal to PWM1 (or PWM2) * (100/255)%: a value of $00 will cause a permanently low output, while a value of $FF will cause a permanently high output, and a value of $13 (for example) will cause a waveform with a duty cycle of
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(19*100/255) = 7.45%. The PWM blocks can be used as simple D/A converters by smoothing the outputs with suitable off-chip low-pass filters. The contents of the PWM1 or PWM2 registers are sampled only at the beginning of each cycle of the output square wave. The microcontroller is therefore able to update the PWM1 and PWM2 registers at any time without affecting the current cycle; the change will only be seen after the current cycle has completed. 1.5.7.1 PWM Control Register (PWMCON) PWMCON: SFR Address $DD Bits b7-6 are cleared to 0 on reset. Other bits are unused, and are 0. Bit:
7 PWM2 enable 6 PWM1 enable 5 4 3 2 1 0
Unused, always read as 0
PWMCON Register b7: PWM 2 Enable b7 = 1 b7 = 0 Enable PWM 2 Disable and reduce power PWM 2
PWMCON Register b6: PWM 1 Enable b6 = 1 b6 = 0 Enable PWM 1 Disable and reduce power PWM 1
PWMCON Register b5-0: Unused 1.5.7.2 PWM Data Registers (PWM1, PWM2) PWM1: SFR Address $DE All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Duty cycle for PWM 1
PWM2: SFR Address $DF All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Duty cycle for PWM 2
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1.5.8
Analogue to Digital Converter
Figure 6 Analogue to Digital Converter Block Diagram The Analogue to Digital Converter (ADC) is a 10-bit successive approximation type converter that produces an unsigned digital representation of an input voltage, selected from one of two input pins, in the range of AVSS to VREF. The ADC output data is stored in two SFRs, ADCBUFL and ADCBUFH. The ADC can be used to do one-shot conversions on command, or it can be used in a continuous convert mode with a selectable sample rate of up to approximately 20kHz. A digital comparator can also be enabled which will generate an interrupt request to the 8051 C if the conversion value enters or leaves certain threshold levels, as set in the SFRs ADCTHRL and ADCTHRH. This can be used with continuous convert mode to automatically monitor a signal level, with no intervention by the 8051 C being required. Other features of the ADC include left- or right-hand justified conversion data, power saving features, optional on-chip track/hold circuits, and a choice between a bandgap-derived voltage reference (VREF = 2.5V) or a supply reference (VREF = AVDD). The selected VREF voltage is driven off chip for user reference through the VREF pin. Note that VINA and VINB are sensitive analogue inputs, and should be carefully decoupled to AVSS to reduce noise and instability in readings.
1.5.8.1 ADC Control Registers (ADCCON1/2) The ADC has two control registers in the SFR space, ADCCON1 and ADCCON2. When low power consumption is important and the ADC is not being used, the internal bandgap reference must be disabled by setting b2 of ADCCON1 to 0 and the track/hold circuits should both be disabled by setting b3 and b2 of ADCCON2 to 0. The 10-bit ADC converter circuit consumes no power between conversions.
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ADCCON1: SFR Address $E2 All bits cleared to 0 on reset. Bit:
7 Threshold high interrupt clear 6 Threshold high interrupt status 5 Threshold low interrupt clear 4 Threshold low interrupt status 3 Inverted threshold mode 2 VREF control 1 Continuous convert enable 0 Manual start & status
ADCCON1 Register b7: Threshold high Interrupt clear Writing a 1 to this bit clears ADCCON1 bit 6 (threshold high interrupt status). ADCCON1 bit 7 always reads back as a 0. ADCCON1 Register b6: Threshold high interrupt status At the end of each ADC conversion, bits 9-2 of the ADC output data are compared against the contents of the ADCTHRH register. Depending on the results of this comparison (see the description of the inverted threshold mode bit, ADCCON1 bit 3), this may cause the threshold high interrupt status bit to be set to 1. If this happens, the Int5 interrupt input of the 8051 C is asserted (pulled low). Because both the threshold high and low interrupt bits are combined to drive a single interrupt line to the 8051 C, this bit must be examined by software if it is necessary to determine which of the two threshold comparators caused the interrupt. The threshold high interrupt status bit is read-only, and can only be cleared by writing 1 to ADCCON1 bit 7. b6 = 1 b6 = 0 Threshold high interrupt active Threshold high interrupt inactive
ADCCON1 Register b5: Threshold low interrupt clear Writing a 1 to this bit clears ADCCON1 bit 4 (threshold low interrupt status). ADCCON1 bit 5 always reads back as a 0. ADCCON1 Register b4: Threshold low interrupt status At the end of each ADC conversion, bits 9-2 of the ADC output data are compared against the contents of the ADCTHRL register. Depending on the results of this comparison (see the description of the inverted threshold mode bit, ADCCON1 bit 3), this may cause the threshold low interrupt status bit to be set to 1. If this happens, the Int5 interrupt input of the 8051 C is asserted (pulled low). Because both the threshold high and low interrupt bits are combined to drive a single interrupt line to the 8051 C, this bit must be examined by software if it is necessary to determine which of the two threshold comparators caused the interrupt. The threshold low interrupt status bit is readonly and can only be cleared by writing 1 to ADCCON1 bit 5. b4 = 1 b4 = 0 Threshold low interrupt active Threshold low interrupt inactive
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ADCCON1 Register b3: Inverted threshold mode This bit selects the conditions for setting the threshold high/low interrupt status bits at the end of an ADC conversion. It is possible to configure the comparators to indicate either when the ADC output value goes outside the range defined by ADCTHRL/ADCTHRH, or when the ADC output value enters that range (the most significant 8 bits of the ADC value are used in the comparison). b3 = 1 b3 = 0 Threshold high and low interrupt status both set to 1 if ADC value ADCTHRH and ADCTHRL Threshold high interrupt status set to 1 if ADC value > ADCTHRH Threshold low interrupt status set to 1 if ADC value < ADCTHRL
If ADCCON1 bit 3 = 1, then both threshold status bits (ADCCON1 bit 6 and bit 4) get set simultaneously, and must both be cleared to remove the interrupt. It is possible to prevent the threshold high/low interrupt status bits from being set to 1 by setting ADCCON bit 3 to 0, ADCTHRH to $FF, and ADCTHRL to $00. If, however, it is desired to always generate an interrupt after a conversion (e.g. when in continuous convert mode), this can be done by setting ADCCON bit 3 to 0, and setting ADCTHRH lower than ADCTHRL. ADCCON1 Register b2: VREF control This bit is used to select the source of the ADC reference voltage; the selected source is also driven onto the VREF pin. If the internal track/hold circuitry is used in conjunction with AVDD as a reference voltage, it may not be possible to obtain correct digital representations for input voltages that are very close to AVDD itself. b2 = 1 b2 = 0 Use the on-chip 2.5V reference for the ADC Use AVDD as the ADC voltage reference, and power save the on-chip 2.5V reference generator
ADCCON1 Register b1: Continuous convert enable This bit is used to enable continuous convert operation, when the ADC will automatically perform conversions at a rate selected in the ADCCON2 register. This may be used in conjunction with the threshold high/low comparators to perform signal monitoring without loading the 8051 C. If required, however, continuous convert can be used without the threshold comparator interrupt being enabled. In this case, the Status bit (ADCCON1 bit 0) will have to be polled to determine when each conversion ends. The data in the ADCBUFL and ADCBUFH registers can then be retrieved, before the next conversion begins. b1 = 1 b1 = 0 Continuous convert enabled Continuous convert disabled
ADCCON1 Register b0: Manual start and status This bit is written with a 1 to start an ADC conversion (writing a 0 has no effect). It may then be read to determine when a conversion has completed, which will be within 156 cycles of the main system clock (equivalent to thirteen 8051 machine cycles or about 14.1s if using an 11.0592MHz crystal): the status bit will read as a 1 while the conversion is taking place, and read as a 0 upon completion. During this time, the ADCBUFL and ADCBUFH registers will contain invalid data. The status bit can also be monitored in continuous convert mode; it is set to 1 when a conversion is started, and cleared to 0 when it ends. It is recommended that ADCCON1 bit 0 is not written with a 1 while continuous convert is enabled, since the timing of the conversions and power save operations may be affected. It may, however, be read from at any time to determine status.
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ADCCON2: SFR Address $E3 All bits cleared to 0 on reset. Bit:
7 Output data left/right justify 6 5 4 3 Powersave track/hold A 2 Powersave track/hold B 1 Auto powersave 0 Input select
Continuous convert sample rate
ADCCON2 Register b7: Output data left/right justify The output from the ADC is 10-bit, requiring two SFRs (ADCBUFL and ADCBUFH) to hold the data. The SFRs therefore contain 6 spare bits, which are set to 0. ADCCON2 bit 7 determines whether the 10-bit ADC conversion result is left- or right-justified within the ADCBUFL and ADCBUFH registers. If the ADC is required for 8-bit conversions only, set this bit to 0 (left-justified), and then only ADCBUFH needs to be read for the valid eight bit data, which is the most significant eight bits of the conversion. b7 = 1 Right-justify ADC data: ADCBUFH 7 6 5 4 3 2 (set to 0)
1
0
7
ADCBUFL 6 5 4 3 2 ADC data bits 9-0
1
0
b7 = 0
Left-justify ADC data: ADCBUFH 7 6 5 4 3 2 1 ADC data bits 9-0
0
7
6
5
ADCBUFL 4 3 2 (set to 0)
1
0
ADCCON2 Register b6-4: Continuous convert sample rate These three bits select the rate at which conversions are done when continuous convert is enabled. b6 0 0 1 1 X b5 0 1 0 1 X b4 1 1 1 1 0 Conversion rate = System clock frequency / 8832 Conversion rate = System clock frequency / 4416 Conversion rate = System clock frequency / 2208 Conversion rate = System clock frequency / 1104 Conversion rate = System clock frequency / 552
ADCCON2 Register b3: Power-save track/hold A This bit is used to explicitly enable the track/hold A circuit, or power save and bypass it if the track/hold function is not required or VINA is not being used. Track/hold A can also be power saved between manual conversions to minimise power consumption, in which case it should be enabled at least 25s before a conversion is done on pin VINA. Power saving track/hold A using ADCCON2 bit 3 overrides the auto power save feature in continuous convert mode (see ADCCON2 bit 1). Hold mode is selected automatically at the start of a conversion. The track/hold circuit returns to Track mode when the conversion is complete. b3 = 1 b3 = 0 Enable track/hold A Power save and bypass track/hold A
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ADCCON2 Register b2: Power-save track/hold B This bit is used to explicitly enable the track/hold B circuit, or power save and bypass it if the track/hold function is not required or VINB is not being used. Track/hold B can also be power saved between manual conversions to minimise power consumption, in which case it should be enabled at least 25s before a conversion is done on pin VINB. Power saving track/hold B using ADCCON2 bit 2 overrides the auto power save feature in continuous convert mode (see ADCCON2 bit 1). Hold mode is selected automatically at the start of a conversion. The track/hold circuit returns to Track mode when the conversion is complete. b2 = 1 b2 = 0 Enable track/hold B Power save and bypass track/hold B
ADCCON2 Register b1: Auto power save This bit can be used to enable the auto power save feature when in continuous convert mode. This causes both track/hold circuits to power down between conversions, and power up again in time for each new conversion. To further save power when using continuous convert mode, the unused ADC input should have its track/hold circuit disabled using ADCCON2 bit 2 or 3. b1 = 1 b1 = 0 Enable auto power save for continuous convert mode Disable auto power save for continuous convert mode
ADCCON2 Register b0: Input select Selects which of the two ADC input channels is used for a conversion. This bit should not be changed while a conversion is in progress, otherwise an invalid result will be obtained. b0 = 1 b0 = 0 Select pin VINB Select pin VINA
1.5.8.2 ADC Buffer Registers (ADCBUFL/H) These two 8-bit buffer registers hold the 10-bit result from an ADC conversion. The data can be selected as left- or right-hand justified by using ADCCON2 bit 7. These registers are not cleared on reset; the data remains unknown until the first conversion is finished. The data is also invalid during each conversion. ADCBUFL: SFR Address $E4 Bit:
Right justified: Left justified: 7 6 5 4 3 2 1 0
ADC data bits 7-0 ADC data bits 1-0 0 0 0 0 0 0
ADCBUFH: SFR Address $E5 Bit:
Right justified: Left justified: 7 0 6 0 5 0 4 0 3 0 2 0 1 0
ADC data bits 9-8
ADC data bits 9-2
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1.5.8.3 ADC Threshold Registers (ADCTHRL/H) At the end of each ADC conversion, bits 9-2 of the ADC output data is compared against the contents of both the ADCTHRL and ADCTHRH registers, which may set the threshold high/low interrupt status bits (see the description of ADCCON1 bits 7-3). ADCTHRL: SFR Address $E6 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
ADC low threshold value
ADCTHRH: SFR Address $E7 All bits cleared to 0 on reset. Bit:
7 6 5 4 3 2 1 0
ADC high threshold value
1.5.9
C-BUS Controller
The C-BUS controller provides for the transfer of data and control between the 8051 C and the DSP modem's internal registers over the C-BUS interface. The modem, described in full in section 1.6, has its own registers that must be accessed using the C-BUS controller to allow the modem to operate as required. Each transaction consists of a minimum of one byte sent from the C, which may be followed by one or more data byte(s) sent from the C to be written into one of the modem's Write Only Registers, or one or more byte(s) of data read out from one of the modem's Read Only Registers, as illustrated below. The C-BUS controller is accessed by the 8051 C through two SFRs, one for read/write data (CBUSBUF) and the other for control (CBUSCON). A transaction is initiated when the 8051 C sets the C-BUS select bit in the CBUSCON register to 1. Command and data bytes may then be sent to the modem by writing to the CBUSBUF register, which the C-BUS controller automatically shifts out to the modem. At the same time, any reply data from the modem gets shifted back into the CBUSBUF register. To read a data byte from the modem, therefore, the 8051 C must perform a dummy byte write to the CBUSBUF register after the initial write of a C-BUS Command to supply Reply Data. Reply data is stored in CBUSBUF every time a byte is written, but is only valid when reading a register. Setting the C-BUS select bit in the CBUSCON register to 0 terminates a transaction. The time between one transaction being terminated and another being initiated may be as small as a single 8051 machine cycle (i.e. 12 system clock cycles). Data bytes may be written to the modem via the CBUSBUF register using back-to-back MOV instuctions. However, when reading a data byte from the modem, at least one machine cycle (e.g. a NOP instruction) must be inserted between the dummy CBUSBUF write and the CBUSBUF data read in order to give the modem time to respond. Failure to do this will result in corruption of the data being read from the modem. The modem also generates an active low interrupt output signal, IRQN, which is configured through a CBUS register within the modem. This IRQN signal is directly connected to the 8051 C's Int3 interrupt input. This signal may also be polled by reading the CBUSCON register.
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a) Single byte (General Reset $01) MOV CBUSCON, #01h MOV CBUSBUF, #01h MOV CBUSCON, #00h b) Write 8-bit reg (address $E3) with one data byte ($55) MOV MOV MOV MOV CBUSCON, CBUSBUF, CBUSBUF, CBUSCON, #01h #0E3h #55h #00h
c) Write 16-bit reg (address $E1) with 2 data bytes ($AC and $BC) MOV MOV MOV MOV MOV CBUSCON, CBUSBUF, CBUSBUF, CBUSBUF, CBUSCON, #01h #0E1h #0ACh #0BCh #00h
d) Read 8-bit reg (address $E5) and store byte in Accumulator MOV MOV MOV NOP MOV MOV CBUSCON, #01h CBUSBUF, #0E5h CBUSBUF, #00h ; Dummy write A, CBUSBUF CBUSCON, #00h
e) Read 16-bit reg (address $E6) and store two bytes @R0 MOV MOV MOV NOP MOV MOV INC MOV MOV CBUSCON, #01h CBUSBUF, #0E6h CBUSBUF, #00h ; Dummy write @R0, CBUSBUF CBUSBUF, #00h ; Dummy write R0 @R0, CBUSBUF CBUSCON, #00h
Table 5 Example of each of the five types of C-BUS transaction
1.5.9.1 C-BUS Control Register (CBUSCON) CBUSCON: SFR Address $EA b0 cleared to 0 on reset. b2-1 are read only. Bit:
7 0 6 0 5 0 4 0 3 0 2 IRQ 1 X 0 C-BUS select
CBUSCON Register b7-3: Unused, set to 0
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CBUSCON Register b2: IRQ This bit is an inverted form of the IRQN output from the modem that is connected to the 8051 C's Int3 interrupt input. This register bit is read-only. b2 = 1 b2 = 0 IRQN active IRQN inactive
CBUSCON Register b1: Reserved bit for internal use. This bit is reserved for internal use; its value when read will be indeterminate. CBUSCON Register b0: C-BUS select This bit must be set active to enable a transaction between the 8051 C and the modem, and taken inactive between transactions. A C-BUS transaction comprises a command byte being sent to the modem, followed by the transfer of up to two further bytes to/from the modem. b0 = 1 b0 = 0 C-BUS select active C-BUS select inactive
1.5.9.2 C-BUS Buffer Register (CBUSBUF) CBUSBUF: SFR Address $EB All bits are cleared to 0 on reset Bit:
7 6 5 4 3 2 1 0
Bits 7-0 of buffer data
CBUSBUF Register b7-0: C-BUS data buffer Data written to this buffer immediately gets shifted out to the modem via the C-BUS interface, and is replaced by reply data from the modem. When reading data from the modem, an instruction (single cycle minimum) must be inserted between a CBUSBUF dummy write and the CBUSBUF data read.
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1.5.10 Keyboard Encoder The CMX850 keyboard encoder has the following features: * * * * * * Full N-key rollover, with key debounce and separate press/release indication. 8-character first-in first-out data buffer. Automatic sleep/wake-up option for low-power operation and reduced EMI. 8 row input pins with integral pull-up resistors. Between 1 and 13 column drive pins (up to 16 if using multiplexed memory interface). Fully autonomous operation, interrupt driven.
Enabling the keyboard encoder automatically configures the Port 1 (P1.7-0) pins as row inputs with pull-up resistors, and configures a user-selectable number of Port4 and Port5 pins as open-drain column drivers. This is done without altering the 8051's port control registers. Those port 4 and port 5 pins which are not configured as column drivers remain as general-purpose port pins. When the keyboard encoder is disabled, all column output and row input pins automatically revert to their previous general-purpose port functions. The keyboard matrix scan period is approximately 9.3ms. The CMX850 keyboard encoder does not have an in-built facility for ghost key elimination or auto repeat generation. If these features are required, they should be performed in software by the 8051 C. The keyboard encoder is accessed through the KBCON, KBSTAT and KBBUF SFRs. 1.5.10.1 Keyboard Control Register (KBCON)
KBCON: SFR Address $EC All bits are cleared to 0 on reset. Bit:
7 Enable 6 Autosleep enable 5 4 3 2 1 0
Debounce period
Number of column drivers
KBCON Register b7: Enable b7 = 1 b7 = 0 Enable keyboard encoder (requires 32.768kHz clock to be active) Disable and powersave the keyboard encoder, and clear the data buffer
KBCON Register b6: Auto-sleep enable The auto-sleep function enables the keyboard encoder to enter a low power mode after approximately 50ms of inactivity (i.e. no key pressed). The keyboard scanner automatically resumes operation when a key is pressed. Auto-sleep mode reduces power consumption and EMI in the CMX850. b6 = 1 b6 = 0 Enable auto-sleep Disable auto-sleep
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KBCON Register b5-4: Debounce period These bits determine for how long each key press/release is debounced before being registered. A debounce period of 3 scan cycles is normally adequate. b5 0 0 1 1 b4 0 1 0 1
Reserved 2 scan cycles 3 scan cycles 4 scan cycles
KBCON Register b3-0: Number of column drivers These four bits determine how many column driver pins the keyboard encoder uses. The selected column driver pins are automatically configured as open-drain outputs when the keyboard encoder is enabled, and revert back to their previous configuration if the keyboard encoder is disabled. b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
1 column driver (P4.0) 2 column drivers (P4.1-0) 3 column drivers (P4.2-0) 4 column drivers (P4.3-0) 5 column drivers (P4.4-0) 6 column drivers (P4.5-0) 7 column drivers (P4.6-0) 8 column drivers (P4.7-0) 9 column drivers (P5.0, P4.7-0) 10 column drivers (P5.1-0, P4.7-0) 11 column drivers (P5.2-0, P4.7-0) 12 column drivers (P5.3-0, P4.7-0) 13 column drivers (P5.4-0, P4.7-0) 14 column drivers (P5.5-0, P4.7-0)* 15 column drivers (P5.6-0, P4.7-0)* 16 column drivers (P5.7-0, P4.7-0)*
* Note: Port bits P5.7-5 are only available with a multiplexed memory interface (pin MUXAD = 1) 1.5.10.2 Keyboard Status Register (KBSTAT)
KBSTAT: SFR Address $ED Bit:
7 6 5 4 3 Overflow clear 2 Overflow status 1 Sleep 0 Empty
Unused, always read as 0
KBSTAT Register b7-4: Unused KBSTAT Register b3: Overflow clear Writing a 1 to this bit clears KBSTAT bit 2 (overflow status). KBSTAT bit 3 always reads back as a 0.
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KBSTAT Register b2: Overflow status (read-only) This bit is set to a 1 if the 8-character keyboard data buffer KBBUF overflows, indicating that data has been lost. This register bit will then remain at logic 1 until it is cleared either by writing 1 to the overflow clear bit (KBSTAT bit 3) or by disabling the keyboard encoder using KBCON bit 7. KBSTAT Register b1: Sleep indicator (read-only) This bit is set to a 1 if the keyboard encoder is enabled but has entered sleep mode (this requires KBCON bit 6 to be set), otherwise the sleep indicator bit will be 0. KBSTAT Register b0: Empty flag (read-only) This bit will set to a 0 when the keyboard data buffer KBBUF contains information, indicating that one or more key presses or key releases have been detected, and is set to a 1 after all data has been read from KBBUF. This bit is connected to the 8051 C's Int4 input, allowing the keyboard encoder to be interrupt driven. In this case, Int4 should be configured as a level interrupt rather than edge triggered. 1.5.10.3 Keyboard Buffer Register (KBBUF)
KBBUF: Read-only. SFR Address $EE This read-only register contains information about the location of any key press or release that the keyboard encoder has detected. The keyboard encoder can buffer up to 8 characters; the data is retrieved by repeatedly reading the KBBUF register. Bit:
7 Press / release 6 5 Row Address 4 3 2 1 0
Column address
KBBUF Register b7: Key press/release indication b7 = 1 b7 = 0 Key press detected Key release detected
KBBUF Register b6-4: Row address These bits indicate on which keyboard row a key press or release was detected (000 = row 0, 001 = row 1, etc). KBBUF Register b3-0: Column address These bits indicate on which keyboard column a key press or release was detected (0000 = column 0, 0001 = column 1, etc).
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1.5.11 Watchdog Timer The Watchdog Timer (WDT) can be used to monitor the operation of the CMX850 system. This is achieved by creating a regular WDT refresh within the software; if this refresh does not occur on time, the WDT will assume that the system has hung and will cause a system reset, preceded by an optional interrupt request to the 8051 C. The WDT is configured and controlled through two SFRs, WDTCON and WDTLD. The WDT can be programmed to have a wide range of timeout values: it uses the 32.768kHz reference clock, prescaled by 1, 8, 64 or 256, to increment a 16-bit counter. A watchdog timeout occurs when this counter reaches $FFFF and subsequently overflows. To prevent this happening, the application software should regularly refresh the watchdog, causing the upper eight bits of the counter to be preloaded from the WDTLD register (the lower eight bits of the counter are simultaneously reset to $00). By selecting the clock prescaler division ratio and the WDTLD register value, a timeout value of between approximately 0.0078 seconds and 8.5 minutes can be programmed. The actual timeout period in seconds can be calculated as: Timeout period = (256-WDTLD)*Prescale/128 (where Prescale = 1, 8, 64, or 256)
When a WDT timeout occurs, the CMX850 will be reset immediately unless the WDT has been configured to first generate an interrupt. In that case, the active low Int8 input to the 8051 C will be pulled down when a WDT timeout occurs. If the WDT is then not refreshed by software, the CMX850 will be reset after a further (Prescale *7.843) milliseconds, approximately. Note that if a WDT interrupt has occurred, a refresh must be performed before changing any of the other configuration bits in the WDTCON register; this can be done using an "ORL WDTCON,#02H" instruction. Failure to observe this precaution may cause a spurious reset to be triggered. The optional WDT interrupt gives the C chance to deal with a watchdog timeout before the entire chip is reset. The reset pulse generated by the WDT lasts for between three and four machine cycles. Note that the WDT must be refreshed before being used for the first time after power up. This should be done after the WDTLD register is written and the WDT is enabled, but before the WDT is started. 1.5.11.1 Watchdog Control Register (WDTCON)
WDTCON: SFR Address $F2 WDTCON bit 2 is cleared to 0 only when the device powers up, all other bits are cleared to 0 on reset. Bit:
7 WDT enable 6 5 4 Delayed reset enable 3 2 Timeout status 1 Refresh 0 Start
WDT prescale
0
WDTCON Register b7: WDT enable The WDT enable bit is cleared to 0 whenever a reset occurs, whether from the RESETN pin or from a WDT timeout. This bit must be set to 1 to enable the clock to the WDT circuitry, which then allows the WDT to be started or refreshed. b7 = 1 b7 = 0 Enable WDT (requires 32.768kHz clock to be active) Disable and powersave the WDT
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WDTCON Register b6-5: WDT prescale These two bits are used to select the division ratio for the 32.768kHz clock prescaler which drives the watchdog timeout counter. b6 0 0 1 1 b5 0 1 0 1
Divide by 256 Divide by 64 Divide by 8 Divide by 1
WDTCON Register b4: Delayed reset enable This bit is used to select whether a reset is generated immediately upon a WDT timeout, or whether an interrupt request is first generated. In either mode the timeout status bit is set when the timeout counter overflows and is only cleared by refreshing the WDT. b4 = 1 b4 = 0 Generate interrupt upon WDT timeout, then reset if the overflow is not subsequently cleared Generate reset upon WDT timeout
WDTCON Register b3: Unused, set to 0 WDTCON Register b2: Timeout status The timeout status bit is set to 1 immediately that a WDT timeout occurs. It is not affected by a reset, but is cleared to 0 when the CMX850 first powers up (all other bits of WDTCON are cleared upon reset). This allows the software to determine whether a system reset was the result of a WDT timeout, so that appropriate action may be taken. Software can only clear the timeout status bit by refreshing the WDT. b2 = 1 b2 = 0 Timeout counter has overflowed No timeout has occurred
WDTCON Register b1: Refresh Writing a 1 to this bit refreshes the WDT counter, i.e. it copies the value in the WDTLD register into the most significant eight bits of the WDT timeout counter, and sets the least significant eight bits to $00. Also, if the timeout status bit (WDTCON.2) happens to be 1, refreshing the WDT causes it to be cleared to 0. The refresh bit in the WDTCON register is automatically cleared to 0 after the refresh has happened, which occurs on the first edge of the 32.768kHz clock after the refresh bit is set to a 1. WDTCON Register b0: Start The bit is used to start or stop the WDT. To start the WDT, the WDTCON enable bit must be set to 1 and the 32.768kHz reference clock must be running. b0 = 1 b0 = 0 Start the WDT Stop the WDT
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1.5.11.2
Watchdog Load Register (WDTLD)
WDTLD: SFR Address $F3 All bits are cleared to 0 on reset. This register is used to store the most significant eight bits of the timeout counter preload value. The timeout counter is preloaded with this value when a WDT refresh is applied. The least significant eight bits of the timeout counter are always preloaded with $00. Bit:
7 6 5 4 3 2 1 0
Bits 15 - 8 of timeout counter preload value
1.5.12 Real Time Clock The Real Time Clock (RTC) is an accurate long period timer that uses the 32.768kHz reference clock within the CMX850. The 32-bit binary rollover counter increments once per second, and is very suitable for storing a real time and date using an appropriate software algorithm. The RTC can also generate a regular interrupt request, the repetition rate being selectable between one sixteenth of a second and eight seconds. The RTC has an alarm feature, which is programmed using a separate 32-bit register. 1.5.12.1 RTC Control Register (RTCCON)
RTCCON: SFR Address $FB This register enables and controls the RTC and allows the selection of the time interval between regular interrupts. Bits 7 and 3 of this register are not affected by a reset. All other bits are cleared to 0 on reset. Bit:
7 RTC enable 6 Prescale reset 5 Time interrupt clear 4 Time interrupt status 3 Clock disable 2 1 0
Time interrupt interval select
RTCCON Register b7: RTC enable This bit is used to enable the RTC. It is not affected by a reset; when the CMX850 powers up its value is unknown and it should be set or cleared as required. b7 = 1 b7 = 0 Enable the RTC Disable and powersave the RTC
RTCCON Register b6: Prescale reset The RTC has an internal "fractions of a second" clock prescaler that divides down the 32.768kHz reference clock to provide pulses for the time interrupt request logic and a 1Hz reference signal for the RTC. This prescaler is normally free running, but can be reset and held using this register bit to allow the time value in the RTC to be precisely synchronised to an external time signal. b6 = 1 b6 = 0 Reset and hold internal clock prescaler at zero Allow the RTC clock prescaler to operate
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RTCCON Register b5: Time interrupt clear Writing a 1 to this bit clears RTCCON bit 4 (time interrupt status). RTCCON bit 5 always reads back as a 0. RTCCON Register b4: Time interrupt status This bit indicates whether a time interrupt has occurred. Its inverse is used to drive the (active low) Int6 interrupt line to the 8051 C. The time interrupt status bit cannot be written directly by the 8051 C, but it can be cleared by writing a 1 to RTCCON bit 5. If the time interrupt feature is not required, it should be disabled by clearing the time interrupt enable bit (IE_1 bit 4), and RTCCON bit 4 should be ignored. b4 = 1 b4 = 0 Selected time interval has elapsed, time interrupt active Time interrupt inactive
RTCCON Register b3: Clock disable This bit can be used to prevent the main RTC time counter from incrementing. This is recommended when setting the TIME0/1/2/3 registers to prevent them from incrementing while being set. This bit does not affect the internal fractions of a second prescaler or the time interval interrupts. This bit is not affected by a reset; when the CMX850 powers up its value is unknown and it should be set or cleared as required. b3 = 1 b3 = 0 Prevent the RTC TIME registers from incrementing Allow the RTC TIME registers to increment
RTCCON Register b2-0: Time IRQ Interval Select These 3 bits select the frequency of time interrupt requests. b2 0 0 0 0 1 1 1 1 1.5.12.2 b1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1
Sixteenth of a second interval Eighth of a second interval Quarter of a second interval Half of a second interval One second interval Two second interval Four second interval Eight second interval
RTC Time Registers (TIME0-TIME3)
The RTC stores the time in four SFRs: TIME0, TIME1, TIME2 and TIME3. Each register holds eight bits, with TIME0 holding the least significant eight bits and TIME3 holding the most significant eight bits. RTC TIME0: SFR Address $FC All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 7 - 0 of RTC TIME register
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RTC TIME1: SFR Address $FD All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 15 - 8 of RTC TIME register
RTC TIME2: SFR Address $FE All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 23 - 16 of RTC TIME register
RTC TIME3: SFR Address $FF All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 31 - 24 of RTC TIME register
To use the clock features, bit 7 of RTCCON is set to 1 to enable the RTC. Then bit 3 of RTCCON is set to 1 to stop the clock counter. The four RTC TIME registers can now be written with the required value in seconds, which can be used to represent a time and date with a suitable software algorithm. Once the required value is stored, the clock can be started by clearing bit 3 of RTCCON. Once the time is set and the clock enabled the value stored will be incremented once every second. The RTC operation will not be suspended when a reset occurs as bits 7 and 3 of RTCCON are unaffected by a reset, so the time will continue to be incremented once every second. If the prescale reset (RTCCON bit 6) is set to 1 before the clock is started, then immediately set back to 0 after the clock is started, the internal fractions of a second will be reset to zero and the first increment of the clock will occur after 1 second. However, if the time interrupt feature is already being used as described in the RTC Control Register section above, and it is required to be accurate and continuous, then the "fractions of a second" prescaler must remain running and the prescale reset must not be used. In this case the first increment of the clock will be synchronised to the already continuously running fractions of a second. Note: to read the current 32-bit time value requires four reads, one from each of the four time registers. Since each read takes a finite time there is a small probability that the time value may be incremented between register reads, giving erroneous results. It is therefore recommended that the 32-bit time value be read repeatedly until two successive 32-bit results match (this will normally happen after the first pair of 32bit reads). The value read will then be correct. 1.5.12.3 RTC Alarm Registers (ALM0-ALM3)
The RTC stores the alarm time in four SFRs: ALM0, ALM1, ALM2 and ALM3. Each register holds eight bits, with ALM0 holding the least significant eight bits and ALM3 holding the most significant eight bits. Using the alarm facility is simply a case of setting the required alarm time in ALM0...3. The RTC waits until the current 32-bit time value is equal to or greater than the 32-bit alarm time, then on the next active edge of the 32.768kHz clock will assert the Int7 interrupt line to the 8051 C (i.e. drive it low). As it is recommended that Int7 be configured as a level sensitive interrupt, it is the responsibility of the interrupt service routine to clear the alarm interrupt request either by clearing IE_1 bit 5 or by writing a new 32-bit alarm value to the ALM0...3 SFRs (writing to any of the ALM0...3 registers negates the Int7 signal). If this is not done, the alarm interrupt will re-trigger upon exit of the service routine. Note that a spurious interrupt request may be generated as the ALM0...3 registers are being updated by software, since four write operations are needed. It is therefore recommended that the alarm interrupt enable bit (IE_1 bit 5) be cleared whenever the ALM0...3 registers are being modified.
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There is no status bit in RTCCON for the alarm interrupt signal, therefore should it be necessary to poll the alarm interrupt it must be done from the flag bit in the interrupt control register ICON1B. ALM0: SFR Address $F4 All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 7 - 0 of RTC ALM register
ALM1: SFR Address $F5 All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 15 - 8 of RTC ALM register
ALM2: SFR Address $F6 All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 23 - 16 of RTC ALM register
ALM3: SFR Address $F7 All bits unaffected by reset. Bit:
7 6 5 4 3 2 1 0
Bits 31 - 24 of RTC ALM register
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1.5.13 CAS Tone and FSK Detector for CLI/CIDCW The CAS (CPE alerting signal) tone and FSK detector circuit is driven from the CMX850's line input amplifier. It provides the ability to detect CAS tones (a burst of simultaneous 2130Hz and 2750Hz signals) or to receive FSK signals and to convert them to either bits or bytes of data. The detector operates with low power consumption and with improved Tone Alert performance in the presence of near-end signals, making it particularly suitable for off-hook CIDCW (Calling Identity on Call Waiting) detection. Note that the CAS/FSK detector uses the same VBIAS generator and line input amplifier as the modem, but is otherwise independent of the modem operation; both can be enabled simultaneously. This may be useful in certain applications, for example when it is necessary to simultaneously look for both DTMF and FSK signals. The CAS/FSK detector is accessed through the CASDET and FSKBUF SFRs. 1.5.13.1 CAS Tone Detector
The detector will function as a CAS Tone Alert detector when the Mode bit (CASDET b6) is set to 0. When in this mode, the Detect bit (CASDET b0) will be set high while a Tone Alert signal is detected. If the Detect signal stays high for a time within the CAS qualifying time TqCAS (see section 1.7.1.3), then on the falling edge of the Detect signal the interrupt status bit in the CASDET SFR will go high. This also asserts the Int2 signal to the 8051 C. The action of writing a 1 to the CAS Tone interrupt clear bit in CASDET generates a short pulse that clears the interrupt status bit. The TqCAS timing is selectable, allowing detection of up to 135 ms Tone Alert (CAS) signals, but is mainly optimised for detection of 75 to 85 ms Tone Alert (CAS) signals used in off-hook applications. Note that Tton added to TqCAS determines the range of times for which the tones should be present for a CAS interrupt to be generated. The TqCAS time range is selected through the Tone Detect Window Control bits in the CASDET SFR. See section 1.7.1.3 for definitions of Tdon and Tdoff and TqCAS.
Figure 7a CAS Tone Alert Detector Operation 1.5.13.2 FSK Detector
The detector will function as a 1200 baud FSK receiver when the Mode bit (CASDET b6) is set to a 1. When in this mode, the detect bit (CASDET b0) will be set high when the FSK signal has exceeded a preset threshold for sufficient time. Amplitude and time hysteresis are used to reduce chattering on the detect bit in marginal conditions. Note that in FSK receive mode the detector may also respond to non-FSK signals such as speech.
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Line Signal DETECT Bit (b0,CASDET)
Teon
FSK signal Teoff
Figure 7b FSK Level Detector Operation 1.5.13.3 FSK Demodulator
When FSK mode is selected (CASDET b6 = 1) the received signal is processed by an FSK demodulator. What happens to the output of this demodulator depends on whether "bit" mode or "byte" mode operation is selected. In bit mode (CASDET b3 = 1) the demodulator output is directly connected to b7 of FSKBUF and the interrupt status bit in the CASDET SFR is tied low (inactive). The user can therefore directly access the FSK signal by polling b7 of the FSKBUF register. In byte mode (CASDET b3 = 0) the FSKBUF register will be indeterminate until the FSK retiming logic has extracted a valid character (8 data bits framed by a start and a stop bit). When a valid character has been received, the 8 data bits are loaded into FSKBUF and the interrupt status bit in the CASDET SFR goes high, which also asserts the Int2 signal to the 8051 C. This alerts the user to read the FSKBUF register. As soon as FSKBUF has been read by the 8051 C, the interrupt is immediately cleared, and the FSKBUF register will again become indeterminate until the next character is received. It should be noted that for correct operation it is necessary to read the FSKBUF register within approximately 8.3ms (the time of a complete character at 1200 baud) otherwise the data will be lost and replaced by the next valid byte of data. If byte mode is enabled during an FSK Channel Seizure signal (a sequence of alternating mark and space bits) it will interpret the signal as valid receive characters, with values of 55 (hex). Similarly it may interpret speech or other signals as random characters. 1.5.13.4 Detect Control Register (CASDET)
CASDET: SFR Address $E9 All Bits are cleared to 0 on reset. Bit:
7 Detector Enable 6 Mode = CAS (0) 5 4 3 2 CAS Interrupt clear 0 1 Interrupt status 0 Detect
CAS Tone Detect Window Control 0 0 Bit Mode Select
Mode = FSK (1)
CASDET Register b7: Detector enable This bit is used to enable the CAS/FSK detector circuit, and to power up the VBIAS generator and line input amplifier in the modem circuit (if not already powered up).
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b7 = 1 b7 = 0
Enable detector Disable and powersave the detector
CASDET Register b6: Mode Select This bit is used to select either CAS Tone Alert Mode or FSK Receiver Mode. The state of this bit determines the function of the remaining bits in this register. b6 = 1 b6 = 0 FSK Receiver Mode CAS Tone Alert Mode
CASDET Register b5-3 (In CAS Mode): Tone Detect Window Control CASDET Register b5-3 (In FSK Mode): Bit Mode Select In CAS mode, the tones being detected are required to last between certain time limits before being considered as valid CAS tones. This time window can be programmed by these register bits to give nominal values, as shown below. The detect window will always start at 65 ms but can be configured to finish between 100 ms and 135 ms in 5 ms divisions. In FSK mode these bits are used to configure the FSK demodulator into bit mode or byte mode (see description in section 1.5.13.3). CAS MODE b5 b4 0 0 0 0 0 1 0 1 1 0 1 0 1 1 1 1
b3 0 1 0 1 0 1 0 1
Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65 Valid Detect Tone Length 65
- 100 ms - 105 ms - 110 ms - 115 ms - 120 ms - 125 ms - 130 ms - 135 ms
FSK MODE b5 b4 b3 0 0 0 0 0 1
FSK byte mode FSK bit mode
CASDET Register b2 (In CAS Mode): CAS interrupt clear CASDET Register b2 (In FSK Mode): Unused, set to 0 In CAS mode, writing a 1 to this bit generates a short pulse that clears CASDET bit 1 (CAS interrupt status). CASDET bit 2 always reads back as a 0. CASDET Register b1: Interrupt status (read-only) In CAS Tone Alert mode this bit indicates whether CAS tones of the correct duration have been received. In FSK Receive mode it indicates that a complete byte is ready to read from FSKBUF (assuming byte mode has been selected). The inverse of this bit is used to drive the (active low) Int2 interrupt line to the 8051 C. The Interrupt status bit cannot be written directly by the 8051 C, but it can be cleared by writing a 1 to CASDET bit 2 in CAS Tone Alert Mode, or by reading the FSKBUF register in FSK Mode. The 8051 C can enable or disable the the interrupt by setting or clearing the Int2 enable bit (IE_1 bit 0). b1 = 1 b1 = 0 Interrupt active (CAS tone detected with correct duration or FSK byte ready) Interrupt inactive
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CASDET Register b0: Detect (read-only) In CAS Tone Alert mode, this bit shows when valid CAS tones are being received, see figure 7a. In FSK Receive mode it shows when valid FSK tones are being received, see figure 7b. This bit can be monitored during a CLI message transaction to minimise falsing, as described in section 1.5.13.6. b0 = 1 b0 = 0 1.5.13.5 FSK signal or CAS tone pair present FSK signal or CAS tone pair not present FSK Buffer Register (FSKBUF)
FSKBUF: Read-only. SFR Address $D1 All bits are cleared to 0 on reset. Bit: 7 FSKBuffer Bit 7 or FSK Demodulator O/P FSKBUF Register b7: FSK Buffer Bit 7 or FSK Demodulator Output When using FSK bit mode, this bit is permanently connected to the FSK demodulator output. In byte mode, this bit will only be valid when a valid byte has been received. This bit will then hold bit 7 of the received byte until it has been read by the user, then the bit will become indeterminate until the next valid byte is stored. FSKBUF Register b6-0: FSK Buffer Bits 6-0 These bits are only valid when FSK byte mode is enabled and the interrupt status bit (CASDET b1) is high to indicate that a valid FSK byte has been received. The received byte is stored in FSKBUF b7-0 until it is read by the 8051 C (see section 1.5.13.3). 1.5.13.6 Example of Using the Detector for Off Hook operations 6 5 4 3 2 1 0
FSK Buffer Bits 6-0
The CASDET block uses the VBIAS generator and line input amplifier within the modem, but is otherwise independent of the modem operation. On receipt of a valid CAS Tone Alert, it will be necessary for the 8051 C to "wake up" the modem and sent the necessary acknowledgement. In this example FSK data is sent from the Central Office, so either the modem or the alternative FSK demodulator can be used for the subsequent data reception. If it is not known whether FSK or DTMF is being used for the data transfer, then the modem can be set to receive DTMF while the CAS /FSK Detector is set to Mode 1 to receive FSK. An example of a message transaction is shown in figure 7c.
Signals originating from far end CPE and Central Office Signals originating at near end CPE
far voice
CAS
FSK data
far voice
ACK A B C D E
near voice F
A. B.
Normal conversation with both near and far end voice present. Central Office mutes far end voice, sends CAS and becomes silent.
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C. D. E. F.
CAS Tone Alert detected and interrupt generated, which causes the CMX850 to mute near end voice, and check that no further CAS tones are detected for 50ms (to minimise falsing) Modem set up to send ACK to Central Office to signal readiness to receive FSK data. Central Office recognises ACK and sends FSK data. The CMX850 is set up to receive the FSK data. The Transaction is complete. The CMX850 unmutes the near voice, and reverts back to its origianal mode, while the central office unmutes the far end voice, normal conversation returns. Figure 7c Typical off-hook (Type 2) message transaction
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1.5.14 1.5.14.1
8051 Accumulator, Flags and Stack Pointer Accumulator Registers (A,B)
A (ACC): SFR Address $E0 All bits reset to 0 on reset. This register is bit addressable. Bit:
7 6 5 4 3 2 1 0
Bits 7 - 0 of the A register
The main accumulator register A is used in a large number of register-specific arithmetic, logical and data transfer instructions. No address byte is needed to point to it, the opcode itself does that. Instructions that refer to the main accumulator as A assemble as accumulator-specific instructions. The A register is also mapped into the 8051 SFR space, and can be read or written using direct addressing. Instructions that refer to the accumulator as ACC will access the accumulator using direct addressing. For example, the instructions MOV R0,A and MOV R0,ACC will both copy the contents of the accumulator to register R0, but will assemble as different opcodes - in this example the main difference is that the instruction MOV R0,A assembles as a 1 byte opcode rather than 2, and executes in 1 machine cycle rather than 2. B: SFR Address $F0 All bits reset to 0 on reset. This register is bit addressable. Bit:
7 6 5 4 3 2 1 0
Bits 7 - 0 of the B register
Register B is mapped into the 8051 SFR space, but is also used implicitly in the MUL AB and DIV AB instructions. The B register is commonly used by programmers as an auxiliary register to store temporary data. 1.5.14.2 Program Status Word Register (PSW)
PSW: SFR Address $D0 All bits reset to 0 on reset. This register is bit addressable. Bit:
7 Carry flag (CY) 6 Auxiliary Carry flag (AC) 5 General purpose flag 0 (F0) 4 Register bank select 1 (RS1) 3 Register bank select 0 (RS0) 2 Overflow flag (OV) 1 General purpose flag 1 (F1) 0 Parity flag (P)
PSW Register b7: Carry flag (CY) During ADD, ADDC or SUBB instructions, this bit gets set if there is a carry-out from bit 7, and cleared otherwise. The Carry flag is also affected by certain other arithmetic, logical and program branching instructions, and also acts as a single bit "accumulator" for a number of the Boolean manipulation instructions.
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PSW Register b6: Auxiliary Carry flag (AC) During ADD, ADDC or SUBB instructions, this bet gets set if there is a carry-out from bit 3, and cleared otherwise. Gets used by the DAA instruction. PSW Register b5: General purpose flag 0 (F0) PSW Register b4-3: Register Bank Select bits (RS1, RS0) These bits are used to select one of the four register banks. b4 0 0 1 1 b3 0 1 0 1
Bank 0 selected, R0-7 mapped to hex address $00-$07 Bank 1 selected, R0-7 mapped to hex address $08-$0F Bank 2 selected, R0-7 mapped to hex addresss $10-$17 Bank 3 selected, R0-7 mapped to hex address $18-$1F
PSW Register b2: Overflow flag (OV) During ADD, ADDC or SUBB instructions, this bit gets set to indicate the sign of the result (i.e. ACC bit 7) is incorrect and is cleared otherwise. This assumes that the two operands are signed integers in the range -128 to 127. More specifically, an overflow occurs if there is a carry-out from bit 6 but not bit 7, or a carry-out from bit 7 but not bit 6. If the two operands are assumed to be unsigned integers in the range 0-255, the overflow flag can be ignored. The overflow flag also gets set by the MUL AB instruction if the product is greater than 255, otherwise it is cleared. The DIV AB instruction always clears the overflow flag. PSW Register b12: General purpose flag (F1) PSW Register b0: Parity flag (P) Set/cleared by hardware each instruction cycle to indicate an odd/even number of "1" bits in accumulator A. 1.5.14.3 Stack Point Register (SP)
SP: SFR Address $81 Bits b7-3 cleared to 0 on reset. Bits b2-0 set to 1 on reset. Bit:
7 6 5 4 3 2 1 0
Bits 7 - 0 of the SP register
The SP register is used as a pointer to the top of the stack area within the 256-byte local RAM. Temporary program data can be stored and retrieved from the stack using the PUSH and POP instructions. When data is pushed onto the stack, the stack pointer is incremented before the data is written. When data is popped off the stack, the stack pointer is decremented after the data is read. The stack also gets used to automatically store the 2-byte return address for subroutine calls and interrupt routines: the low-order byte of the return address gets pushed onto the stack first, then the high order byte. Stack accesses use indirect addressing to the local RAM, which means that all 256 bytes of the local RAM can be utilised by the stack.
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1.5.15 1.5.15.1
Timers and Serial Port Timer/Counter Control Register (TCON)
TCON: SFR Address $88 All bits reset to 0 on reset. This register is bit addressable. Bit:
7 Timer 1 overflow flag (TF1) 6 Timer 1 run control (TR1) 5 Timer 0 overflow flag (TF0) 4 Timer 0 run control (TR0) 3 Int1 edge flag (IE1) 2 Int1 type control (IT1) 1 Int0 edge flag (IE0) 0 Int0 type control (IT0)
TCON Regsiter b7: Timer 1 overflow flag (TF1) The Timer 1 overflow flag gets set to 1 by hardware when Timer 1 overflows, and gets cleared automatically when the Timer 1 interrupt service routine is called. TCON Register b6: Timer 1 run control bit (TR1) b6 = 1 b6 = 0 Turn Timer/Counter 1 on Turn Timer/Counter 1 off
TCON Register b5: Timer 0 overflow flag (TF0) The Timer 0 overflow flag gets set to 1 by hardware when Timer 0 overflows, and gets cleared automatically when the Timer 0 interrupt service routine is called. TCON Register b4: Timer 0 run control bit (TR0) b4 = 1 b4 = 0 Turn Timer/Counter 0 on Turn Timer/Counter 0 off
TCON Register b3: Int1 edge flag (IE1) When Int1 is configured as falling edge triggered, this bit is set to 1 by hardware to indicate that an edge has been detected (i.e. successive samples of the Int1 pin show a high in one machine cycle and a low in the next cycle) and gets cleared automatically when the Int1 service routine is called. When configured as a low level triggered interrupt, the edge flag will be updated once per cycle to reflect the state of the Int1 pin; the flag gets set to 1 if the Int1 pin is active (i.e. low), and gets cleared to 0 if the Int1 pin is inactive (high). TCON Register b2: Int1 type control (IT1) b2 = 1 b2 = 0 Int1 configured as a falling edge triggered interrupt Int1 configured as a low level triggered interrupt.
TCON Register b1: Int0 edge flag (IE0) When Int0 is configured as falling edge triggered, this bit is set to 1 by hardware to indicate that an edge has been detected (i.e. successive samples of the Int0 pin show a high in one machine cycle and a low in the next cycle) and gets cleared automatically when the Int0 service routine is called. When configured as a low level triggered interrupt, the edge flag will be updated once per cycle to reflect the state of the Int0 pin: the flag gets set to 1 if the Int0 pin is active (i.e. low), and gets cleared by 0 if the Int0 pin is inactive (high).
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TCON Register b0: Int0 type control (IT0) b0 = 1 b0 = 0 1.5.15.2 Int0 configured as a falling edge triggered interrupt Int0 configured as a low level triggered interrupt. Timer/Counter Mode Register (TMOD)
TMOD: SFR Address $89 All bits reset to 0 on reset. Bit:
7 Timer 1 gate 6 Timer 1 C/T control 5 Timer 1 mode select 1 4 Timer 1 mode select 0 3 Timer 0 gate 2 Timer 0 C/T control 1 Timer 0 mode select 1 0 Timer 0 mode select 0
TMOD Register b7: Timer 1 gate b7 = 1 b7 = 0 Timer/Counter 1 only runs while TCON.6 (TR1) = 1 and Int1 is high (hardware control) Timer/Counter 1 only runs while TCON.6 (TR1) = 1 (software control)
TMOD Register b6: Timer 1 C/T control b6 = 1 b6 = 0 Counter operation (input from T1 input pin) Timer operation (input from internal system clock)
TMOD Register b5-4: Timer 1 mode select b5 0 0 1 1 b4 0 1 0 1
13-bit timer/counter (TH1 = 8-bit counter, TL1 = 5-bit prescaler) 16-bit timer/counter 8-bit Auto-reload timer/counter (TH1 = reload value, TL1 = 8-bit counter) Does not run
TMOD Register b3: Timer 0 gate b3 = 1 b3 = 0 Timer/Counter 0 only runs while TCON.4 (TR0) = 1 and Int0 is high (hardware control) Timer/Counter 0 only runs while TCON.4 (TR0) = 1 (software control)
TMOD Register b2: Timer 0 C/T control b2 = 1 b2 = 0 Counter operation (input from T0 to input pin) Timer operation (input from internal system clock)
TMOD Register b1-0: Timer 0 mode select b1 0 0 1 1 b0 0 1 0 1
13-bit timer/counter (TH0 = 8-bit counter, TL0 = 5-bit prescaler 16-bit timer/counter 8-bit Auto-reload timer (TH0 = reload value, TL0 = 8-bit counter) Two 8-bit timers, TL0 and TH0: TL0 uses timer 0 control bits, TH0 is locked into a timer function (counting machine cycles) and takes over the use of TR1, TF1 and the Timer 1 interrupt.
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1.5.15.3
Timer/Counter Registers (TL0, TL1, TH0, TH1)
TL0: SFR Address $8A - All bits reset to 0 in reset Bit:
7 6 5 4 3 2 1 0
Timer/Counter 0 low byte
TL1: SFR Address $8B All bits reset to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Timer/Counter 1 low byte
TH0: SFR Address $8C All bits set to 0 on reset. Bit:
7 6 5 4 3 2 1 0
Timer/Counter 0 high byte
TH1: SFR Address $8D All bits reset to 0 on reset Bit:
7 6 5 4 3 2 1 0
Timer/Counter 1 high byte
1.5.15.4
Serial Port Control Register (SCON)
SCON: SFR Address $98 All bits reset to 0 on reset. This register is bit addressable. Bit:
7 Serial port mode select 0 (SM0) 6 Serial port mode select 1 (SM1) 5 Serial port mode select 2 (SM2) 4 Serial port receive enable (REN) 3 9 transmit data bit (TB8)
th
2 9 received data bit (RB8)
th
1 Transmit interrupt flag (TI)
0 Receive interrupt flag (RI)
SCON Register b7-6: Serial port mode select 0-1 (SM0, SM1) b7 0 0 1 1 b6 0 1 0 1
Serial port mode 0 (shift register, baud rate = fosc/12) Serial port mode 1 (8-bit UART, baud rate = variable) Serial port mode 2 (9-bit UART, baud rate = fosc/64 or fosc/32) Serial port mode 3 (9-bit UART, baud rate = variable)
In mode 1 or 3 the baud rate is generated by Timer 1, according to the formula Baud Rate = (K * fosc) / (32 * 12 * (256-TH1)) Where K = 1 if SMOD = 0, and K = 2 if SMOD = 1 (SMOD is bit 7 of the PCON register). The frequency of fosc is that of the main xtal oscillator divided by the clock speed reduction programmed into bits 0-2 of the SPDCON register ($9D). fosc is used to count or time the values programmed into Timer 0 and Timer 1.
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SCON Register b5: Serial port mode select 2 (SM2) Enables the multiprocessor communications feature in modes 2 and 3: if SM2 = 1 then RI will not be activated if the 9th received data bit (RB8) is 0. In mode 1, if SM2 = 1 then RI will not be activated if a valid stop bit was not received. In mode 0, SM2 should be 0. SCON Register b4: Serial port receive enable (REN) b4 = 1 b4 = 0 Enable serial reception Disable serial reception
SCON Register b3: 9th transmitted data bit (TB8) In modes 2 and 3, this is the 9th data bit that will be transmitted. Set or cleared by software as desired. SCON Register b2: 9th received data bit (RB8) In modes 2 and 3, this is the 9th data bit that was received. In mode 1, if SM2 = 0, this is the stop bit that was received. In mode 0, this bit is not used. SCON Register b1: Transmit interrupt flag (TI) Set by hardware at the end of the 8th bit time in mode 0, or at the beginning of the stop bit in other modes, in any serial transmission. Must be cleared by software. SCON Register b0: Receive interrupt flat (RI) Set by hardware at the end of the 8th bit time in mode 0, or halfway through the stop bit time in other modes, in any serial reception (except see SM2). Must be cleared by software. 1.5.15.5 Serial Port Buffer Register (SBUF)
SBUF: SFR Address $99 All bits indeterminate on reset.
Bit:
7
6
5
4
3
2
1
0
Bits 7-0 of the SBUF register
The serial port is full duplex, i.e. it can transmit and receive simultaneously. The transmit and receive registers are both accessed through the SBUF SFR. Reading SBUF will access the serial port receive register (the serial port has a one-byte deep receive buffer, allowing reception of a second byte to commence before the previously received byte has been read). Writing to SBUF initiates a serial port transmission.
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1.6
Modem General Description
The Modem transmit and receive operating modes are independently programmable. The transmit mode can be set to any one of the following: V.22 bis modem. 2400bps QAM (Quadrature Amplitude Modulation). V.22 and Bell 212A modem. 1200 or 600 bps DPSK (Differential Phase Shift Keying). V.21 modem. 300bps FSK (Frequency Shift Keying). Bell 103 modem. 300bps FSK. V.23 modem. 1200 or 75 bps FSK. Bell 202 modem. 1200 or 150 bps FSK. DTMF transmit. Single tone transmit (from a range of modem calling, answer and other tone frequencies) User programmed tone or tone pair transmit (programmable frequencies and levels) Disabled. The receive mode can be set to any one of the following: V.22 bis modem. 2400bps QAM. V.22 and Bell 212A modem. 1200 or 600 bps DPSK. V.21 modem. 300bps FSK. Bell 103 modem. 300 bps FSK. V.23 modem. 1200 or 75 bps FSK. Bell 202 modem. 1200 or 150 bps FSK. DTMF detect. 2100Hz and 2225Hz answer tone detect. Call progress signal detect. User programmed tone or tone pair detect. Disabled. The Modem may also be set into a Powersave mode which disables all circuitry except for the C-BUS interface, the Ring Detector and the Hook Detector.
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Figure 8 Modem Block Diagram
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1.6.1
Tx USART
A flexible Tx USART is provided for all modem modes, meeting the requirements of V.14 for QAM and DPSK modems. It can be programmed to transmit continuous patterns, Start-Stop characters or Synchronous Data. In both Synchronous Data and Start-Stop modes the data to be transmitted is written by the C into the 8-bit C-BUS Tx Data Register from which it is transferred to the Tx Data Buffer. If Synchronous Data mode has been selected the 8 data bits in the Tx Data Buffer are transmitted serially, b0 being sent first. In Start-Stop mode a single Start bit is transmitted, followed by 5, 6, 7 or 8 data bits from the Tx Data Buffer - b0 first - followed by an optional Parity bit then - normally - one or two Stop bits. The Start, Parity and Stop bits are generated by the USART as determined by the Tx Mode Register settings and are not taken from the Tx Data Register.
Figure 9a Tx USART Every time the contents of the C-BUS Tx Data Register are transferred to the Tx Data Buffer the Tx Data Ready flag bit of Status Register 1 is set to 1 to indicate that a new value should be loaded into the C-BUS Tx Data Register. This flag bit is cleared to 0 when a new value is loaded into the Tx Data Register.
Figure 9b Tx USART Function (Start-Stop mode, 8 Data Bits + Parity) If a new value is not loaded into the Tx Data Register in time for the next Tx Data Register to Tx Data Buffer transfer then Status Register 1 Tx Data Underflow bit will be set to 1. In this event the contents of the Tx Data Buffer will be re-transmitted if Synchronous Data mode has been selected, or if the Tx modem is in Start-Stop mode then a continuous Stop signal (1) will be transmitted until a new value is loaded into the Tx Data Register. In all modes the transmitted bit and baud rates are the nominal rates for the selected modem type, with an accuracy determined by the accuracy of the system clock frequency, however for QAM and DPSK modes V.14 requires that Start-Stop characters can be transmitted at up to 1% overspeed (basic signalling rate
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range) or 2.3% overspeed (extended signalling rate range) by deleting a Stop bit from no more than one out of every 8 (basic range) or 4 (extended range) consecutive transmitted characters. To accommodate the V.14 requirement the Tx Data Register has been given two C-BUS addresses, $E3 and $E4. Data should normally be written to $E3. In QAM or DPSK Start-Stop modes if data is written to $E4 then the programmed number of Stop bits will be reduced by one for that character. In this way the C can delete transmitted Stop bits as needed. In FSK Start-Stop modes, data written to $E4 will be transmitted with a 12.5% reduction in the length of the Stop bit at the end of that character. In all Synchronous Data modes data written to $E4 will be treated as though it had been written to $E3. The underspeed transmission requirement of V.14 is automatically met by the Modem as in Start-Stop mode it automatically inserts extra Stop bit(s) if it has to wait for new data to be loaded into the C-BUS Tx Data Register. The optional V.22/V.22 bis compatible data scrambler can be programmed to invert the next input bit in the event of 64 consecutive ones appearing at its input. It uses the generating polynomial: 1 + x-14 + x-17
1.6.2
FSK and QAM/DPSK Modulators
Serial data from the USART is fed via the optional scrambler to the FSK modulator if V.21, V.23, Bell 103 or Bell 202 mode has been selected or to the QAM/DPSK modulator for V.22, V.22 bis and Bell 212A modes. The FSK modulator generates one of two frequencies according to the transmit mode and the value of current transmit data bit. The QAM/DPSK modulator generates a carrier of 1200Hz (Low Band, Calling modem) or 2400Hz (High Band, Answering modem) which is modulated at 600 symbols/sec as described below: 600bps V.22 signals are transmitted as a +90 carrier phase change for a `0' bit, +270 for `1'. For V.22 and Bell 212A 1200bps DPSK the transmit data stream is divided into groups of two consecutive bits (dibits) which are encoded as a carrier phase change: Dibit (left-hand bit is the first of the pair) 00 01 11 10
Phase change +90 0 +270 +180
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For V.22 bis 2400bps QAM the transmit data stream is divided into groups of 4 consecutive data bits. The first two bits of each group are encoded as a phase quadrant change and the last two bits define one of four elements within a quadrant: First two bits of group (left-hand bit is the first of the pair) 00 01 11 10
Phase quadrant change +90 (e.g. quadrant 1 to 2) 0 (no change of quadrant) +270 (e.g. quadrant 1 to 4) +180 (e.g. quadrant 1 to 3)
Figure 10 V.22 bis Signal Constellation
1.6.3
Tx Filter and Equaliser
The FSK or QAM/DPSK modulator output signal is fed through the Transmit Filter and Equaliser block which limits the out-of-band signal energy to acceptable limits. In 600, 1200 and 2400 bps FSK, DPSK and QAM modes this block includes a fixed compromise line equaliser which is automatically set for the particular modulation type and frequency band being employed. This fixed compromise line equaliser may be enabled or disabled by bit 10 of the General Control Register. The amount of Tx equalisation provided compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1 over the frequency band used.
1.6.4
DTMF/Tone Generator
In DTMF/Tones mode this block generates DTMF signals or single or dual frequency tones. In QAM/DPSK modem modes it is used to generate the optional 550 or 1800Hz guard tone.
1.6.5
Tx Level Control and Output Drivers
The Modem generated signal (if present) from the FSK/DTMF/Tones Generator is passed through the programmable Tx Level Control before being passed to the switched paths controlled by the Analogue Signal Path Register. The Tx Output drivers have symmetrical outputs to provide sufficient line voltage swing at low values of AVDD and to reduce harmonic distortion of the signal. The drivers can also transmit the signal from the other port (e.g. Phone Input to Line Driver) or can be independently set to VBIAS or Powersaved - see the description of the Analogue Signal Path Register.
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1.6.6
DTMF Decoder and Tone Detectors
In Rx Tones Detect mode the received signal, after passing through the Rx Gain Control block, is fed to the DTMF decoder and Programmable Tone Pair/Call Progress/Answer Tone detectors. The user may select one of four separate operations: The DTMF decoder detects standard DTMF signals. A valid DTMF signal will set bit 5 of Status Register 1 to 1 for as long as the signal is detected. The DTMF signal is then decoded and output in bits 0 to 3 of Status Register 1. The programmable tone pair detector includes two separate tone detectors (see Figure 15a). The first detector will set bit 6 of Status Register 1 for as long as a valid signal is detected, the second detector sets bit 7, and bit 10 of Status Register 1 will be set when both tones are detected. The frequency and bandwidth of each detector can be set in the Programming Register. Without programming, the default values in the Programming Register are set for the detection of 2130Hz and 2750Hz. The Call Progress detector measures the amplitude of the signal at the output of a 275 Hz - 665 Hz bandpass filter and sets bit 10 of Status Register 1 to 1 when the signal level exceeds the measurement threshold.
10 0 -10 -20 dB -30 -40 -50 -60 0 0.5 1 1.5 2 kHz 2.5 3 3.5 4
Figure 11a Response of the Call Progress Filter The Answer Tone detector measures both amplitude and frequency of the received signal and sets bit 6 or bit 7 respectively of Status Register 1 when a valid 2225Hz or 2100Hz signal is received.
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1.6.7
Rx Modem Filtering and Demodulation
When the receive part is operating as a modem, the received signal is fed to a bandpass filter to attenuate unwanted signals and to provide fixed compromise line equalisation for 600, 1200 and 2400 bps FSK, DPSK and QAM modes. The characteristics of the bandpass filter and equaliser are determined by the chosen receive modem type and frequency band. The line equaliser may be enabled or disabled by bit 10 of the General Control Register and compensates for one quarter of the relative amplitude and delay distortion of ETS Test Line 1. The responses of these filters, including the line equaliser and the effect of external components used in Figures 4a and 4b, are shown in Figures 11b-e:
10 0 -10 -20 -30 -40 -50 -60 0 0.5 1 1.5 kHz 2 2.5 3 3.5 4 10 0 -10 -20 -30 -40 -50 -60 0 0.5 1 1.5 kHz 2 2.5 3 3.5 4
dB
dB
Figure 11b QAM/DPSK Rx Filters
10 0 -10 -20 -30 -40 -50 -60 0 0.5 1 1.5 kHz 2 2.5 3 3.5 4 10 0 -10 -20 -30 -40 -50 -60 0 0.5
Figure 11c V.21 Rx Filters
dB
dB
1
1.5 kHz
2
2.5
3
3.5
4
Figure 11d Bell 103 Rx Filters
Figure 11e V.23/Bell 202 Rx Filters
The signal level at the output of the Receive Modem Filter and Equaliser is measured in the Modem Energy Detector block, compared to a threshold value, and the result controls bit 10 of Status Register 1. The output of the Receive Modem Filter and Equaliser is also fed to the FSK or QAM/DPSK demodulator, depending on the selected modem type. The FSK demodulator recognises individual frequencies as representing received `1' or `0' data bits. The QAM/DPSK demodulator decodes QAM or DPSK modulation of a 1200Hz or 2400Hz carrier and is used for V.22, V.22 bis and Bell 212A modes. It includes an adaptive receive signal equaliser (autoequaliser) that will automatically compensate for a wide range of line conditions in both QAM and DPSK modes. The auto-equaliser can provide a useful improvement in performance in 600 or 1200bps DPSK
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modes as well as 2400bps QAM, so although it must be disabled at the start of a handshake sequence, it can be enabled as soon as scrambled 1200bps 1s have been detected. Both FSK and QAM/DPSK demodulators produce a serial data bit stream which is fed to the Rx pattern detector, descrambler and USART block, see Figure 12a. In QAM/DPSK modes the demodulator input is also monitored for the V.22 bis handshake `S1' signal. The QAM/DPSK demodulator also estimates the received bit error rate by comparing the actual received signal against an ideal waveform. This estimate is placed in bits 2-0 of Status Register 1, see Figure 14.
1.6.8
Rx Modem Pattern Detectors and Descrambler
See Figure 12a. The 1010.. pattern detector operates only in FSK modes and will set bit 9 of Status Register 1 when 32 bits of alternating 1's and 0's have been received. The `Continuous Unscrambled 1's' detector operates in all modem modes and sets bits 8 and 7 of Status Register 1 to `01' when 32 consecutive 1's have been received. The descrambler operates only in DPSK/QAM modes and is enabled by setting bit 7 of the Rx Mode Register. The `Continuous Scrambled 1's' detector operates only in DPSK/QAM modes when the descrambler is enabled and sets bits 8 and 7 of Status Register 1 to `11' when 32 consecutive 1's appear at the output of the descrambler. To avoid possible ambiguity, the `Scrambled 1's' detector is disabled when continuous unscrambled 1's are detected. The `Continuous 0's' detector sets bits 8 and 7 of Status Register 1 to `10' when NX consecutive 0's have been received, NX being 32 except when DPSK/QAM Start-Stop mode has been selected, in which case NX = 2N + 4 where N is the number of bits per character including the Start, Stop and any Parity bits. All of these pattern detectors will hold the `detect' output for 12 bit times after the end of the detected pattern unless the received bit rate or operating mode is changed, in which case the detectors are reset within 2 msec.
1.6.9
Rx Data Register and USART
A flexible Rx USART is provided for all modem modes, meeting the requirements of V.14 for QAM and DPSK modems. It can be programmed to treat the received data bit stream as Synchronous data or as Start-Stop characters. In Synchronous mode the received data bits are all fed into the Rx Data Buffer which is copied into the C-BUS Rx Data Register after every 8 bits. In Start-Stop mode the USART Control logic looks for the start of each character, then feeds only the required number of data bits (not parity) into the Rx Data Buffer. The parity bit (if used) and the presence of a Stop bit are then checked and the data bits in the Rx Data Buffer copied to the C-BUS Rx Data Register.
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Figure 12a Rx Modem Data Paths Whenever a new character is copied into the C-BUS Rx Data Register, the Rx Data Ready flag bit of Status Register 1 is set to `1' to prompt the C to read the new data and, in Start-Stop mode, the Even Rx Parity flag bit of Status Register 1 is updated. In Start-Stop mode, if the Stop bit is missing (received as a `0' instead of a `1') the received character will still be placed into the Rx Data Register and the Rx Data Ready flag bit set, but, unless allowed by the V.14 overspeed option described below, Status Register 1 Rx Framing Error bit will also be set to `1' and the USART will re-synchronise onto the next `1' - `0' (Stop - Start) transition. The Rx Framing Error bit will remain set until the next character has been received.
Figure 12b Rx USART Function (Start-Stop mode, 8 Data Bits + Parity) If the C has not read the previous data from the Rx Data Register by the time that new data is copied to it from the Rx Data Buffer then the Rx Data Overflow flag bit of Status Register 1 will be set to 1. The Rx Data Ready flag and Rx Data Overflow bits are cleared to 0 when the Rx Data Register is read by the C. For QAM and DPSK Start-Stop modes, V.14 requires that the receive USART be able to cope with missing Stop bits; up to 1 missing Stop bit in every 8 consecutive received characters being allowed for the +1% overspeed (basic signalling rate) V.14 mode and 1 in 4 for the +2.3% overspeed (extended signalling rate) mode. To accommodate the requirements of V.14, the Modem Rx Mode Register can be set for 0, +1% or +2.3% overspeed operation in QAM or DPSK Start-Stop modes. Missing Stop bits beyond those allowed by the selected overspeed option will set the Rx Framing Error flag bit of Status Register 1. In order that received Break signals can be handled correctly in V.14 Rx overspeed mode, a received character which has all bits `0', including the Stop and any Parity bits, will always cause the Rx Framing Error bit to be set and the USART to re-synchronise onto the next `1' - `0' transition. Additionally the received Continuous 0s detector will respond when more than 2M + 3 consecutive `0's are received, where `M' is the selected total number of bits per character including Stop and any Parity bits.
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1.6.10 Analogue Signal Routing The routing of signals to and from the Line and Phone interfaces is performed by bits 0 to 5 of the Analogue Signal Path Register. Note that bits 6 and 7 of this register are reserved for future use and should be set to zero.
1.6.11 C-BUS Interface This block provides for the transfer of data and control or status information between the Modem's internal registers and the C over the C-BUS serial bus. This interface is controlled by the C-BUS Controller, which is part of the C and is described in section 1.5.9. The following C-BUS addresses and registers are used by the Modem: General Reset Command (address only, no data). General Control Register, 16-bit write only. Transmit Mode Register, 16-bit write-only. Receive Mode Register, 16-bit write-only. Transmit Data Register, 8-bit write only. Receive Data Register, 8-bit read-only. Status Register 1, 16-bit read-only. Status Register 2, 16-bit read-only. Programming Register, 16-bit write-only. Analogue Signal Path Register, 8-bit write-only. Address $01 Address $E0 Address $E1 Address $E2 Address $E3 and $E4 Address $E5 Address $E6 Address $E7 Address $E8 Address $EC
Notes: 1. The C-BUS addresses $E9, $EA and $EB are allocated for production testing and should not be accessed in normal operation. 2. In several registers there are bit patterns whose function is not specified. These modes should not be accessed in normal operation and no guarantee is given that any use of these bits will be supported in the future. 1.6.11.1 General Reset Command (no data) C-BUS address $01
General Reset Command
This command resets the modem and clears all bits of the General Control, Analogue Signal Path, Programming, Transmit Mode and Receive Mode Registers and all bits of Status Register 1 except b14 and Status Register 2 except b8. The clearing of the General Control Register will put the modem into Powersave. See the description of General Control Register b8 for the procedure on how to power-up the modem. Whenever power is applied a General Reset command should be sent to the modem, after which the General Control Register should be set as required. The xtal frequency should also be configured using the 8051 OSCCON special function register before the modem is used.
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1.6.11.2
General Control Register C-BUS address $E0
General Control Register: 16-bit write-only.
This register controls general features of the modem such as the Powersave mode, the IRQ mask bits and the Relay Drive output. It also allows the fixed compromise equalisers in the Tx and Rx signal paths to be disabled if desired. All bits of this register are cleared to 0 by a General Reset command. Bit:
15 0 14 0 13 0 12 0 11 Hook IRQ Mask 10 Equ 9 Rly drv 8 Pwr 7 Rst 6 Irqn en 5 4 3 2 1 0
IRQ Mask Bits
General Control Register b15-12: Reserved, set to 0000 General Control Register b11: Hook Detect IRQ Mask bit This bit affects the operation of the IRQ bit of Status Register 1 as described in section 1.6.11.8 General Control Register b10: Tx and Rx Fixed Compromise Equaliser This bit allows the Tx and Rx fixed compromise equaliser in the modem transmit and receive filter blocks to be disabled. b10 = 1 b10 = 0 Disable equaliser Enable equaliser (1200bps modem mode)
General Control Register b9: Relay Drive This bit directly controls the RDRVN output pin. b9 = 1 b9 = 0 RDRVN output pin pulled to DVSS RDRVN output pin pulled to DVDD
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General Control Register b8: Powerup This bit controls the internal power supply to most of the internal circuits, including the VBIAS supply. Note that the General Reset command clears this bit, putting the device into Powersave mode. b8 = 1 b8 = 0 Device powered up normally Powersave mode (all circuits except Ring Detect, Hook Detect, RDRVN and C-BUS interface disabled)
When power is first applied to the device, the following powerup procedure should be followed to ensure correct operation. i. ii. iii. (Power is applied to the device) Issue a General Reset command or momentarily set the RESETN pin low. Write to the General Control Register (address $E0) setting both the Powerup bit (b8) and the Reset bit (b7) to 1 - leave in this state for a minimum of about 20ms - it is required that the system clock initially runs for this time in order to clock the internal logic into a defined state. The device is now powered up, with the VBIAS supply operating, but is otherwise not running any transmit or receive functions. Set the Xtal frequency to the correct one in the OSCCON register, if necessary see section 1.5.6.1 The device is now ready to be programmed as and when required. Examples: * A General Reset command could be issued to clear all the registers and therefore powersave the device. * The Reset bit in the General Control Register could be set to 0 as part of a routine to program all the relevant registers for setting up a particular operating mode.
iv. v.
When the modem is switched from Powersave mode to normal operation by setting the Powerup bit to 1, the Reset bit should also be set to 1 and should be held at 1 for about 20ms with the system clock running, allowing the VBIAS supply to stabilise, before starting to use the transmitter or receiver.
General Control Register b7: Reset Setting this bit to 1 resets the modem's internal circuitry, clearing all bits of the Analogue Signal Path, Programming, Transmit and Receive Mode Registers and b13-0 of Status Register 1. b7 = 1 b7 = 0 Internal circuitry in a reset condition. Normal operation
General Control Register b6: IRQNEN (IRQN Enable) Setting this bit to 1 enables the Modems IRQN signal. b6 = 1 b6 = 0 IRQN driven low (to DVSS) if the IRQ bit of Status Register 1 = 1 IRQN disabled (set to 1)
General Control Register b5-0: IRQ Mask bits These bits affect the operation of the IRQ bit of Status Register 1 as described in section 1.6.11.8
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D/850/6
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CMX850
1.6.11.3
Transmit Mode Register C-BUS address $E1
Transmit Mode Register: 16-bit write-only.
This register controls the Modem transmit signal type and level. All bits of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit:
15 14 13 12 11 10 Tx level Tx level 9 8 7 6 5 4 3 2 1 0
Tx mode = modem Tx mode = DTMF/Tones Tx mode = Disabled
Guard tone
Scrambler
DTMF twist Set to 0000 0000 0000
Start-stop / # data bits / synch data synch data source DTMF or Tone select
Tx Mode Register b15-12: Tx mode These 4 bits select the transmit operating mode. b15 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 b14 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 b13 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 b12 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 V.22 bis 2400 bps QAM " V.22/Bell 212A 1200 bps DPSK " V.22 600 bps DPSK " V.21 300 bps FSK " Bell 103 300 bps FSK " V.23 FSK " Bell 202 FSK " DTMF / Tones Transmitter disabled High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) High band (Answering modem) Low band (Calling modem) 1200 bps 75 bps 1200 bps 150 bps
Tx Mode Register b11-9: Tx level These 3 bits set the gain of the Tx Level Control block. b11 1 1 1 1 0 0 0 0 b10 1 1 0 0 1 1 0 0 b9 1 0 1 0 1 0 1 0 0dB -1.5dB -3.0dB -4.5dB -6.0dB -7.5dB -9.0dB -10.5dB
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Tx Mode Register b8-7: Tx Guard tone (QAM, DPSK modes) These 2 bits select the guard tone to be transmitted together with highband QAM or DPSK. Set both bits to 0 in FSK modes. b8 b7 1 1 Tx 550Hz guard tone 1 0 Tx 1800Hz guard tone 0 x No Tx guard tone Tx Mode Register b6-5: Tx Scrambler (QAM, DPSK modes) These 2 bits control the operation of the Tx scrambler used in QAM and DPSK modes. Set both bits to 0 in FSK modes. b6 b5 1 1 Scrambler enabled, 64 ones detect circuit enabled (normal use) 1 0 Scrambler enabled, 64 ones detect circuit disabled 0 x Scrambler disabled Tx Mode Register b4-3: Tx Data Format (QAM, DPSK, FSK modes) These two bits select Synchronous or Start-stop mode and the addition of a parity bit to transmitted characters in Start-stop mode. b4 1 1 0 0 b3 1 0 1 0
Synchronous mode Start-stop mode, no parity Start-stop mode, even parity bit added to data bits Start-stop mode, odd parity bit added to data bits
Tx Mode Register b2-0: Tx Data and Stop bits (QAM, DPSK, FSK Start-Stop modes) In Start-stop mode these three bits select the number of Tx data and stop bits. b2 1 1 1 1 0 0 0 0 b1 1 1 0 0 1 1 0 0 b0 1 0 1 0 1 0 1 0
8 data bits, 2 stop bits 8 data bits, 1 stop bit 7 data bits, 2 stop bits 7 data bits, 1 stop bit 6 data bits, 2 stop bits 6 data bits, 1 stop bit 5 data bits, 2 stop bits 5 data bits, 1 stop bit
Tx Mode Register b2-0: Tx Data source (QAM, DPSK, FSK Synchronous mode) In Synchronous mode (b4-3 = 11) these three bits select the source of the data fed to the Tx FSK or QAM/DPSK scrambler and modulator. b2 1 0 0 0 b1 x 1 1 0 b0 x 1 0 x
Data bytes from Tx Data Buffer Continuous 1s Continuous 0s Continuous V.22 bis handshake S1 pattern dibits '00,11' in DPSK and QAM modes, continuous alternating 1s and 0s in all other modes.
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CMX850
Tx Mode Register b8: DTMF Twist (DTMF mode) If DTMF/Tones transmit mode has been selected (Tx Mode Register b15-12 = 0001) then set this bit to 0 and set the twist in b7-5 (000 default = +2.0dB). Tx Mode Register b7-5: DTMF Twist (DTMF mode) These 3 bits allow for adjustment of the DTMF twist to compensate for the frequency response of different external circuits. The CMX850 varies the twist by making changes to the upper tone group levels. Note that the twist cannot adjusted mid-tone. b7 0 0 0 0 1 1 1 1 b6 0 0 1 1 0 0 1 1 b5 0 1 0 1 0 1 0 1 +2.0dB twist - normal setting when external response is flat +1.0dB twist +1.5dB twist +2.5dB twist +3.0dB twist +3.5dB twist +4.0dB twist +4.5dB twist - do not use in conjunction with the 0dB Tx level setting
Tx Mode Register b4-0: DTMF/Tones mode If DTMF/Tones transmit mode has been selected (Tx Mode Register b15-12 = 0001) then b4-0 will select a DTMF signal or a fixed tone or one of four programmed tones or tone pairs for transmission. b4 = 0: Tx fixed tone or programmed tone pair b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Tone frequency (Hz) No tone 697 770 852 941 1209 1336 1477 1633 1300 2100 2225 Tone pair TA Tone pair TB Tone pair TC Tone pair TD
(Calling tone) (Answer tone) (Answer tone) Programmed Tx tone or tone pair, see section 1.6.11.10 " " "
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CMX850
b4 = 1: Tx DTMF b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Low frequency (Hz) 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852 High frequency (Hz) 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633 Keypad symbol D 1 2 3 4 5 6 7 8 9 0 * # A B C
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D/850/6
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CMX850
1.6.11.4
Receive Mode Register C-BUS address $E2
Receive Mode Register: 16-bit write-only.
This register controls the modem receive signal type and level. All bits of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit:
15 14 13 12 11 10 Rx level Rx level 9 8 Eq 7 6 5 4 3 2 1 0
Rx mode = modem Rx mode = Tones detect Rx mode = Disabled
No. of bits and parity DTMF/Tones/Call Progress select Set to 0000 0000 0000
Descrambl
Start-stop/Synch
Rx Mode Register b15-12: Rx mode These 4 bits select the receive operating mode. b15 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 b14 1 1 1 1 0 0 0 0 1 1 1 1 0 0 0 0 b13 1 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 b12 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 V.22 bis 2400 bps QAM High band (Calling modem) " Low band (Answering modem) V.22/Bell 212A 1200 bps DPSK High band (Calling modem) " Low band (Answering modem) V.22 600 bps DPSK High band (Calling modem) " Low band (Answering modem) V.21 300 bps FSK High band (Calling modem) " Low band (Answering modem) Bell 103 300 bps FSK High band (Calling modem) " Low band (Answering modem) V.23 FSK 1200 bps " 75 bps Bell 202 FSK 1200 bps " 150 bps DTMF, Programmed tone pair, Answer Tone, Call Progress detect Receiver disabled
Rx Mode Register b11-9: Rx level These three bits set the gain of the Rx Gain Control block. b11 1 1 1 1 0 0 0 0 b10 1 1 0 0 1 1 0 0 b9 1 0 1 0 1 0 1 0 0dB -1.5dB -3.0dB -4.5dB -6.0dB -7.5dB -9.0dB -10.5dB
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Rx Mode Register b8: Rx Auto-equalise (DPSK/QAM modem modes) This bit controls the operation of the receive DPSK/QAM auto-equaliser. Set to 0 in FSK modes. b8 = 1 b8 = 0 Enable auto-equaliser DPSK mode: Auto-equaliser disabled QAM mode : Auto-equaliser settings frozen
Rx Mode Register b7-6: Rx Scrambler (DPSK/QAM modem modes) These 2 bits control the operation of the Rx descrambler used in QAM and DPSK modes. Set both bits to 0 in FSK modes b7 b6 1 1 Descrambler enabled, 64 ones detect circuit enabled (normal use) 1 0 Descrambler enabled, 64 ones detect circuit disabled 0 x Descrambler disabled Rx Mode Register b5-3: Rx USART Setting (QAM, DPSK, FSK modem modes) These three bits select the Rx USART operating mode. The 1% and 2.3% overspeed options apply to DPSK/QAM modes only. b5 b4 b3 1 1 1 Rx Synchronous mode 1 1 0 Rx Start-stop mode, no overspeed 1 0 1 Rx Start-stop mode, +1% overspeed (1 in 8 missing Stop bits allowed) 1 0 0 Rx Start-stop mode, +2.3% overspeed (1 in 4 missing Stop bits allowed) 0 x x Rx USART function disabled Rx Mode Register b2-0: Rx Data bits and parity (QAM, DPSK, FSK Start-Stop modem modes) In Start-stop mode these three bits select the number of data bits (plus any parity bit) in each received character. These bits are ignored in Synchronous mode. b2 b1 b0 1 1 1 8 data bits + parity 1 1 0 8 data bits 1 0 1 7 data bits + parity 1 0 0 7 data bits 0 1 1 6 data bits + parity 0 1 0 6 data bits 0 0 1 5 data bits + parity 0 0 0 5 data bits Rx Mode Register b2-0: Tones Detect mode In Tones Detect Mode (Rx Mode Register b15-12 = 0001) b8-3 should be set to 000000 Bits 2-0 select the detector type. b2 b1 b0 1 0 0 Programmable Tone Pair Detect 0 1 1 Call Progress Detect 0 1 0 2100, 2225Hz Answer Tone Detect 0 0 1 DTMF Detect 0 0 0 Disabled
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CMX850
1.6.11.5
Tx Data Register C-BUS address $E3
2 1 0
Tx Data Register: 8-bit write-only. Bit:
7 6 5 4 3
Data bits to be transmitted
In Synchronous Tx data mode this register contains the next 8 data bits to be transmitted. Bit 0 is transmitted first. In Tx Start-stop mode the specified number of data bits will be transmitted from this register (b0 first). A Start bit, a Parity bit (if required) and Stop bit(s) will be added automatically. This register should only be written to when the Tx Data Ready bit of Status Register 1 is 1. C-BUS address $E3 should normally be used, $E4 is for implementing the V.14 overspeed transmission requirement in Start-Stop mode, see section 1.6.1.
1.6.11.6
Rx Data Register C-BUS address $E5
2 1 0
Rx Data Register: 8-bit read-only. Bit:
7 6 5 4 3
Received data bits
In unformatted Rx data mode this register contains 8 received data bits, b0 of the register holding the earliest received bit, b7 the latest. In Rx Start-stop data mode this register contains the specified number of data bits from a received character, b0 holding the first received bit.
1.6.11.7
Analogue Signal Path Register C-BUS address $EC
Analogue Signal Path Register: 8-bit write-only.
This register controls the routing of the analogue signal paths and controls the output drivers. Bit: 7 0 6 0 5 Aux. Line RXN Enable 4 Line Driver Mode 3 2 1 0 Input Selector Control
Phone Driver Mode
Bits 7-6 of the Analogue Signal Path Register are reserved for future use and should be set to 0. Analogue Signal Path Register b5: Auxiliary Line RXN enable Enables the LINERXBN pin to be connected to the line Rx amp. inverting input (at the same time as the LINERXN pin). Used to increase gain, and compensate for signal attenuation during on-hook CLI detect. b5 = 1 b5 = 0 Aux. Line RXN enabled Aux. Line RXN disabled
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CMX850
Analogue Signal Path Register b4-3: Line Driver Mode These bits control the complementary Line Driver and select the signal to be transmitted. b4 0 0 1 1 b3 0 1 0 1 Line Driver Mode Off / High Impedance Transmit Phone-derived Signal Transmit Modem Generated Signal Transmit Bias Level
Analogue Signal Path Register b2-1: Phone Driver Mode These bits control the complementary Phone Driver and select the signal to be transmitted. b2 0 0 1 1 b1 0 1 0 1 Phone Driver Mode Off / High Impedance Transmit Line-derived Signal Transmit Modem Generated Signal Transmit Bias Level
Analogue Signal Path Register b0: Input Selector Control This bit selects between the Line and Phone as inputs to the modem's decoders/detectors. Note: both op-amps remain powered up even when not selected (unless device is powersaved). b0 = 1 b0 = 0 Notes: 1. `Line-derived signal' means the signal at the output of the Line input op-amp. `Phonederived signal' means the signal at the output of the Phone input op-amp. The `Modem Generated Signal' means the signal from the DTMF/Tones or FSK generators. When the modem is put into Powersave by setting Bit 8 of the General Control Register to 1, the transmit drivers and receive op-amps are powersaved and their outputs go high impedance. The settings of the Analogue Signal Path Register are unaffected, however. Line-derived signal to decoders/detectors Phone-derived signal to decoders/detectors
2.
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D/850/6
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CMX850
1.6.11.8
Status Register 1 C-BUS address $E6
Status Register 1: 16-bit read-only.
Bits 15 and 13-0 of this register are cleared to 0 by a General Reset command, or when b7 (Reset) of the General Control Register is 1. Bit:
15 IRQ 14 RD 13 PF 12 11 10 9 8 7 6 5 4 3 2 1 0
See below for uses of these bits
The meanings of Status Register 1 bits 12-0 depend on whether the receive circuitry is in Modem or Tones Detect mode, as shown in Table 6. Status Register 1 bits: Rx Modem modes b15 b14 b13 b12 b11 b10 Rx Tones Detect modes ** IRQ Mask bit b5 b4 b3 b3 b2
b9
b8 b7
b6
b5
b4 b3 b2 b1 b0
IRQ Set to 1 on Ring Detect Programming Flag bit. See section 1.6.11.10 Set to 1 on Tx data ready. Cleared by write to Tx Data Register Set to 1 on Tx data underflow. Cleared by write to Tx Data Register 1 when energy is detected in Rx 1 when energy is detected in Call modem signal band Progress band or when both programmable tones are detected 0 1 when S1 pattern (double DPSK dibit 00,11) is detected in DPSK or QAM modes, or when `1010..' pattern is detected in FSK modes See following table 0 See following table 1 when 2100Hz answer tone or the second programmable tone is detected Set to 1 on Rx data ready. 1 when 2225Hz answer tone or the Cleared by read from Rx Data first programmable tone is detected Register Set to 1 on Rx data overflow. 1 when DTMFcode is detected Cleared by read from Rx Data Register Set to 1 on Rx framing error 0 Set to 1 on even Rx parity Rx DTMF code b3, see table QAM/DPSK Rx signal quality b2 Rx DTMF code b2 QAM/DPSK Rx signal quality b1 Rx DTMF code b1 QAM/DPSK Rx signal quality b0 Rx DTMF code b0 or FSK frequency demodulator output
b1
b1 b1
b0
b0
-
Notes: ** This column shows the corresponding IRQ Mask bits in the General Control Register. Table 6 Status Register 1 - Bit Allocations Certain events of Status Register 1 bits 14-5 and Status Register 2 bit 8 will cause the IRQ bit b15 to be set to 1 if the corresponding IRQ Mask bit is 1. These events are:
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CMX850
for Status Register 1 Bit 14 (Ring Detect) and Bit 10 (Energy or Call Progress / Programmable Tones Detect) and Status Register 2 Bit 8 (Hook Detect), both positivegoing (0 to 1) and negative-going (1 to 0) transitions, for the remaining Status Register bits, only positive-going (0 to 1) transitions. The IRQ bit is cleared by a read of Status Register 1 or Status Register 2 depending on the source of the IRQ, or a General Reset command or by setting b7 or b8 of the General Control Register to 1. The operation of the data demodulator and pattern detector circuits within the modem does not depend on the state of the Rx energy detect function. Decoding of Status Register 1 b8,7 in Rx Modem Modes (see also Figure 12a): b8 1 1 0 0 b7 1 0 1 0 Descrambler disabled Continuous unscrambled 0s Continuous unscrambled 1s Descrambler enabled (DPSK/QAM modes only) Continuous scrambled 1s (see note) Continuous scrambled 0s Continuous unscrambled 1s -
When the descrambler is enabled then detection of continuous unscrambled 1s will inhibit the continuous scrambled 1s detector.
Figure 13a Operation of Status Register 1 bits 5-10
The IRQN signal will be pulled low when the IRQ bit of Status Register 1 and the IRQNEN bit (b6) of the General Control Register are both 1. Changes to Status Register 1 bits caused by a change of Tx or Rx operating mode can take up to 150s to take effect. In Powersave mode or when the Reset bit (b7) of the General Control Register is 1 the Ring Detect bit (b14) continues to operate. The `continuous 0' and `continuous 1' detectors monitor the Rx signal after the QAM/DPSK descrambler, (see Figure 12a) and hence will detect continuous 1s or 0s if the descrambler is disabled, or continuous scrambled 1s or 0s if the descrambler is enabled.
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D/850/6
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CMX850
In QAM or DPSK Rx modem modes b2-0 of Status Register 1 contain a value indicative of the received signal BER, see Figure 14. In Rx FSK modem modes bits 2 and 1 will be zero and b0 will show the output of the frequency demodulator, updated at 8 times the nominal data rate.
Figure 13b Operation of Status Register 1 in DTMF Rx Mode
b3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1
b2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1
b1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1
b0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1
Low frequency (Hz) 941 697 697 697 770 770 770 852 852 852 941 941 941 697 770 852
High frequency (Hz) 1633 1209 1336 1477 1209 1336 1477 1209 1336 1477 1336 1209 1477 1633 1633 1633
Keypad symbol D 1 2 3 4 5 6 7 8 9 0 * # A B C
Table 7 Received DTMF Code: b3-0 of Status Register 1
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CMX850
1.E-03
1.E-04
BER
1.E-05
1.E-06 0 1 2 3 4 5 6 7
Rx Status Register BER reading
Figure 14 Typical Rx BER vs. Average Status Register 1 BER Reading (b2-0)
1.6.11.9 Status Register 2 Status Register 2: 16-bit read-only. Status Register 2 bits: Rx Modem modes b15-9 b8 b7-0 Rx Tones Detect modes ** IRQ Mask bit b11 C-BUS address $E7
Reserved, will read as 0000000 Set to 1 on Hook Detect Reserved, will read as 00000000
Notes: ** This column shows the corresponding IRQ Mask bit in the General Control Register. A 0 to 1 transition on bit 8 Hook Detect will cause the IRQ bit b15 of Status Register 1 (see previous section) to be set to 1 if the corresponding IRQ Mask bit is 1. If the IRQ bit is generated by Status Register 2 bit 8, it will be cleared by reading Status Register 2 or a General Reset command or by setting b7 or b8 of the General Control Register to 1. Therefore it is recommended that both Status Register 1 and Status Register 2 are read to determine the source of an IRQ. Table 8 Status Register 2 - Bit Allocations
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D/850/6
Communications Controller
CMX850
1.6.11.10
Programming Register C-BUS address $E8
Programming Register : 16-bit write-only.
This register is used to program the transmit and receive programmed tone pairs by writing appropriate values to RAM locations within the modem. Note that these RAM locations are cleared by Powersave or Reset. The Programming Register should only be written to when the Programming Flag bit (b13) of Status Register 1 is 1. The act of writing to the Programming Register clears the Programming Flag bit. When the programming action has been completed (normally within 150s) the modem will set the bit back to 1. When programming Transmit or Receive Tone Pairs, do not change the Transmit or Receive Mode Registers until programming is complete and the Programming Flag bit has returned to 1. Transmit Tone Pair Programming 4 transmit tone pairs (TA to TD) can be programmed. The frequency (max 3.4kHz) and level must be entered for each tone to be used. Single tones are programmed by setting both level and frequency values to zero for one of the pair. Programming is done by writing a sequence of up to seventeen 16-bit words to the Programming Register. The first word should be 32768 (8000 hex), the following 16-bit words set the frequencies and levels and are in the range 0 to 16383 (0-3FFF hex) Word 1 2 3 4 5 6 7 ----14 15 16 17 Tone Pair TA TA TA TA TB TB ----TD TD TD TD Value written 32768 Tone 1 frequency Tone 1 level Tone 2 frequency Tone 2 level Tone 1 frequency Tone 1 level ------------------Tone 1 frequency Tone 1 level Tone 2 frequency Tone 2 level Default Setting
2130 Hz -20 dBm 2750 Hz -20 dBm
The Frequency values to be entered are calculated from the formula: Value to be entered = desired frequency (Hz) * 3.414 i.e. for 1kHz the value to be entered is 3414 (or 0D56 in Hex). The Level values to be entered are calculated from the formula: Value to be entered = desired Vrms * 93780 / AVDD i.e. for 0.5Vrms at AVDD = 3.0V, the value to be entered is 15630 (3D0E in Hex) Note that allowance should be made for the transmit signal filtering in the modem which attenuates the output signal for frequencies above 2kHz by 0.25dB at 2.5kHz, by 1dB at 3kHz and by 2.2dB at 3.4kHz.
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D/850/6
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CMX850
Receive Tone Pair Programming The programmable tone pair detector is implemented as shown in Figure 15a. The filters are 4th order IIR sections. The frequency detectors measure the time taken for a programmable number of complete input signal cycles and compare this time against programmable upper and lower limits. NB. If this register is not programmed, the detector will be configured to operate in its default mode, which is for the detection of 2130 Hz 20 Hz and 2750 Hz 30 Hz tones.
Figure 15a Programmable Tone Detectors
Figure 15b Filter Implementation
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D/850/6
Communications Controller
CMX850
Programming is done by writing a sequence of twenty-seven 16-bit words to the Programming Register. The first word should be 32769 (8001 hex), the following twenty-six 16-bit words set the frequencies and levels and are in the range 0 to 32767 (0000-7FFF hex). Word 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Value written 32769 Filter #1 coefficient b21 Filter #1 coefficient b11 Filter #1 coefficient b01 Filter #1 coefficient a21 Filter #1 coefficient a11 Filter #1 coefficient b22 Filter #1 coefficient b12 Filter #1 coefficient b02 Filter #1 coefficient a22 Filter #1 coefficient a12 Freq measurement #1 ncycles Freq measurement #1 mintime Freq measurement #1 maxtime Word 15 16 17 18 19 20 21 22 23 24 25 26 27 Value written Filter #2 coefficient b21 Filter #2 coefficient b11 Filter #2 coefficient b01 Filter #2 coefficient a21 Filter #2 coefficient a11 Filter #2 coefficient b22 Filter #2 coefficient b12 Filter #2 coefficient b02 Filter #2 coefficient a22 Filter #2 coefficient a12 Freq measurement #2 ncycles Freq measurement #2 mintime Freq measurement #2 maxtime
The coefficients are entered as 15-bit signed (two's complement) integer values (the most significant bit of the 16-bit word entered should be zero) calculated as 8192 * coefficient value from the user's filter design program (i.e. this allows for filter design values of -1.9999 to +1.9999). The design of the IIR filters should make allowance for the fixed receive signal filtering in the Modem which has a low pass characteristic above 1.5kHz of 0.4dB at 2kHz, 1.2dB at 2.5kHz, 2.6dB at 3kHz and 4.1dB at 3.4kHz. `ncycles' is the number of signal cycles for the frequency measurement. `mintime' is the smallest acceptable time for ncycles of the input signal expressed as the number of 9.6kHz timer clocks. i.e. `mintime' = 9600 * ncycles / high frequency limit `maxtime' is the highest acceptable time for ncycles of the input signal expressed as the number of 9.6kHz timer clocks. i.e. `maxtime' = 9600 * ncycles / low frequency limit The level detectors include hysteresis. The threshold levels - measured at a 2-wire line interface with unity gain filters, using typical line interface circuits, 1.0 dB line coupling loss and with the Rx Gain Control block set to 0dB - are nominally: `Off' to `On' `On' to `Off' -44.5dBm -47.0dBm
Note that if any changes are made to the programmed values while the Modem is running in Programmed Tone Detect mode they will not take effect until the Modem is next switched into Programmed Tone Detect mode.
1.6.11.11
Other Registers
C-BUS addresses $E9, $EA and $EB are reserved and should not be accessed.
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D/850/6
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CMX850
1.7
1.7.1
Performance Specification
Electrical Performance
1.7.1.1 Absolute Maximum Ratings Exceeding these maximum ratings can result in damage to the device. Min. Supply (AVDD - AVSS) or (DVDD - DVSS) -0.3 Voltage on any pin (except VCAP) to AVSS or DVSS -0.3 Voltage between AVSS and DVSS Voltage between AVDD and DVDD Current into or out of AVSS, DVSS, AVDD or DVDD pins -50 Current into RDRVN pin (RDRVN pin low) Current into or out of any other pin -20
Max. 4.0 VDD + 0.3 50 300 +50 +50 +20
Units V V mV mV mA mA mA
L8 Package Total Allowable Power Dissipation at Tamb = 25C ... Derating Storage Temperature Operating Temperature 1.7.1.2 Operating Limits
Min.
-55 -40
Max. 1300 27 +125 +85
Units mW mW/C C C
Correct operation of the device outside these limits is not implied. Notes Min. Supply (AVDD - AVSS) or (DVDD - DVSS) 3.0 Rise time (10% - 90%) Operating Temperature -40 Xtal Frequency 0
Max. 3.6 25 +85 12.5
Units V ms C MHz
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1.7.1.3 Operating Characteristics For the following conditions unless otherwise specified: VDD = AVDD = DVDD = 3.0V to 3.6V at Tamb = -40 to +85C, VSS = AVSS = DVSS Xtal Frequency = 11.0592 or 12.288MHz 0.01% (100ppm)1, 0dBm corresponds to 775mVrms. DC Parameters IDD (Zero-Power Mode) (11.0592 MHz Xtal operating, Idle Mode) (32.768 kHz Xtal operating, Idle Mode) (5.5 MHz RC Oscillator only, Idle Mode) (ADC only, excluding 11.0592 MHz Xtal) (CAS Detector and FSK Receiver only, excluding 11.0592MHz Xtal) (Keyboard encoder only, no auto-sleep, no key pressed, excluding 32.768 kHz Xtal) (PWM only, one output at 50%, excluding 11.0592 MHz Xtal) (Real Time Clock [RTC] only, excluding 32.768 kHz Xtal) (Watchdog Timer [WDT] only, excluding 32.768 kHz Xtal) (Modem [Rx, Tx, C-BUS and signal paths] operating, excluding 8051 Core) (8051 Core operating, excluding Modem) (8051 Core operating, including Modem) Logic '1' Input Level Logic '0' Input Level Logic Input Leakage Current (Vin = 0 to DVDD), (excluding XTAL/CLOCK inputs) Output Logic '1' Level - Ports 1, 3, 4, 5 and pin X32KN (configured as output) @ lOH = 1 mA Output Logic '0' Level - Ports 1, 3, 4, 5 and pin X32KN (configured as output) @ lOL = -1.5 mA Output Logic '1' Level - D7-0, A15-0, WEN, OEN, CSN1, CSN2, CSN3 @ lOH = 2 mA Output Logic '0' Level - D7-0, A15-0, WEN, OEN, CSN1, CSN2, CSN3 @ lOL = -3 mA Schmitt triggers input high-going threshold (Vthi) (see Figure 16) Schmitt triggers input low-going threshold (Vtlo) (see Figure 16) RDRVN `ON' resistance to DVSS (DVDD= 3.3V) RDRVN `OFF' resistance to DVDD (DVDD= 3.3V) Port pull-up and Data pin bushold resistance XTAL/CLOCK Input (timing for an external clock input to XTAL pin only) 'High' Pulse Width 'Low' Pulse Width Notes 1, 2 1, 2 1, 2 1, 2 1, 3 1 1 1 1 1 1 1 1 4 4 Min. 70% -1.0 80% 80% 0.56DVDD 0.44DVDD - 0.6V 25 Notes Min. Typ. 6 0.8 7 320 330 350 7 30 6 6 3.5 3.1 6.6 50 1170 50 Typ. Max. 60 16.0 30% +1.0 0.4 0.4 0.56DVDD + 0.6V 0.44DVDD 70 3000 85 Max. Units A mA A A A A A A A A mA mA mA DVDD DVDD A DVDD V DVDD V V V k Units
30 30
-
-
ns ns
1 Only 11.0592MHz supports a standard 19,200 serial port baud rate when executing on-chip BOOT ROM. See section 1.4.4 Local BOOT ROM. (c) 2003 CML Microsystems Plc 92 D/850/6
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Transmit QAM and DPSK Modes (V.22, Bell 212A, V.22 bis) Carrier frequency, high band Carrier frequency, low band Baud rate Bit rate (V.22, Bell 212A) Bit rate (V.22 bis) 550Hz guard tone frequency 550Hz guard tone level wrt data signal 1800Hz guard tone frequency 1800Hz guard tone level wrt data signal Transmit V.21 FSK Mode Baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Transmit Bell 103 FSK Mode Baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Transmit V.23 FSK Mode Baud rate Mark (logical 1) frequency, 1200 baud Space (logical 0) frequency, 1200 baud Mark (logical 1) frequency, 75 baud Space (logical 0) frequency, 75 baud Transmit Bell 202 FSK Mode Baud rate Mark (logical 1) frequency, 1200 baud Space (logical 0) frequency, 1200 baud Mark (logical 1) frequency, 150 baud Space (logical 0) frequency, 150 baud DTMF/Single Tone Transmit Tone frequency accuracy Distortion Transmit Output Level Modem and Single Tone modes DTMF mode, Low Group tones DTMF: level of High Group tones wrt Low Group Tx output buffer gain control accuracy
Notes 5 5 6 6 6
Min. 548 -4.0 1797 -7.0 Min. 1647 1847 978 1178 Min. 2222 2022 1268 1068 Min. 1298 2097 389 449 Min. 1198 2197 386 486 Min. -0.2 Min. -3.2 -1.2 +1.0 -0.25
Typ. 2400 1200 600 1200/600 2400 550 -3.0 1800 -6.0 Typ. 300 1650 1850 980 1180 Typ. 300 2225 2025 1270 1070 Typ. 1200/75 1300 2100 390 450 Typ. 1200/150 1200 2200 387 487 Typ. 1.0 Typ. -2.2 -0.2 +2.0 -
Max. 552 -2.0 1803 -5.0 Max. 1653 1853 982 1182 Max. 2228 2028 1272 1072 Max. 1302 2103 391 451 Max. 1202 2203 388 488 Max. +0.2 2.0 Max. -1.2 +0.8 +3.0 +0.25
Units Hz Hz Baud bps bps Hz dB Hz dB Units Baud Hz Hz Hz Hz Units Baud Hz Hz Hz Hz Units Baud Hz Hz Hz Hz Units Baud Hz Hz Hz Hz Units % % Units dBm dBm dB dB
Notes 6
Notes 6
Notes 6
Notes 6
Notes 7 Notes 7 7 7 7
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Receive QAM and DPSK Modes (V.22, Bell 212A, V.22 bis) Carrier frequency (high band) Carrier frequency (low band) Baud rate Bit rate (V.22, Bell 212A) Bit rate (V.22 bis) Receive V.21 FSK Mode Acceptable baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Receive Bell 103 FSK Mode Acceptable baud rate Mark (logical 1) frequency, high band Space (logical 0) frequency, high band Mark (logical 1) frequency, low band Space (logical 0) frequency, low band Receive V.23 FSK Mode 1200 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency 75 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency Receive Bell 202 FSK Mode 1200 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency 150 baud Acceptable baud rate Mark (logical 1) frequency Space (logical 0) frequency Rx Modem Signal Signal level Signal to Noise Ratio (noise flat 300-3400Hz) Rx Modem S1 Pattern Detector (DPSK and QAM modes) Will detect S1 pattern lasting for Will not detect S1 pattern lasting for Hold time (minimum detector `On' time)
Notes
Min. 2392 1192 Min. 297 1638 1838 968 1168 Min. 297 2213 2013 1258 1058 Min. 1188 1280 2080 74 382 442
Typ. 2400 1200 600 1200/600 2400 Typ. 300 1650 1850 980 1180 Typ. 300 2225 2025 1270 1070 Typ. 1200 1300 2100 75 390 450 Typ. 1200 1200 2200 150 387 487 Typ. Typ. -
Max. 2408 1208 Max. 303 1662 1862 992 1192 Max. 303 2237 2037 1282 1082 Max. 1212 1320 2120 76 398 458 Max. 1212 1220 2220 152 397 497 Max. -9.0 Max. 72.0 -
Units Hz Hz Baud bps bps Units Baud Hz Hz Hz Hz Units Baud Hz Hz Hz Hz Units Baud Hz Hz Baud Hz Hz Units Baud Hz Hz Baud Hz Hz Units dBm dB Units ms ms
9 9 9 Notes
Notes
Notes
Notes
Min. 1188 1180 2180 148 377 477
Notes 10
Min. -45.0 20.0 Min. 90.0 5.0
Notes
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Rx Modem Continuous 1s and 1010.. Pattern Detectors Turn on time Turn off time Rx Modem Energy Detector Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Hysteresis Detect (`Off' to `On') response time 1200 baud FSK mode 150 and 75 baud FSK modes Undetect (`On' to `Off') response time 1200 baud FSK mode 150 and 75 baud FSK modes Rx Answer Tone Detectors Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Detect (`Off' to `On') response time Undetect (`On' to `Off') response time 2100Hz detector `Will detect' frequency `Will not detect' frequency 2225Hz detector `Will detect' frequency `Will not detect' frequency Rx Call Progress Energy Detector Bandwidth (-3dB points) See Figure 11a Detect threshold (`Off' to `On) Undetect threshold (`On' to `Off') Detect (`Off' to `On') response time Undetect (`On' to `Off') response time Receive Input Amplifier Input impedance (at 100Hz) Open loop gain (at 100Hz) Rx Gain Control Block accuracy
Notes
Min. 32 12
Typ. Typ. Typ. 33.0 18.0 Typ. 36.0 8.0 Typ. 10000
Max. 40 20 Max. -43.0 30.0 60.0 40.0 80.0 Max. -43.0 45.0 25.0 2160 2000 2285 Max. 665 -37.0 45.0 50.0 Max.
Units bittimes bittimes Units dBm dBm dB ms ms ms ms Units dBm dBm ms ms Hz Hz Hz Hz Units Hz dBm dBm ms ms Units M V/V dB
Notes 10,11 10,11 10,11 10,11 10,11 10,11 10,11 Notes 10, 12 10, 12 10, 12 10, 12
Min. -48.0 2.0 8.0 16.0 10.0 20.0 Min. -48.0 30.0 7.0 2050 2160 2335
Notes 10,13 10,13 10,13 10,13 Notes
Min. 275 -42.0 30.0 6.0 Min. 10.0 -0.25
+0.25
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DTMF Decoder Valid input signal levels (each tone of composite signal) Not decode level (either tone of composite signal) Twist = High Tone/Low Tone Frequency Detect Bandwidth Max level of low frequency noise (i.e dial tone) Interfering signal frequency <= 550Hz Interfering signal frequency <= 450Hz Interfering signal frequency <= 200Hz Max. noise level with respect to the signal DTMF detect response time DTMF de-response time Status Register b5 high time `Will Detect' DTMF signal duration `Will Not Detect' DTMF signal duration Pause length detected Pause length ignored Tone Alert (CAS) Detector `Low' Tone nominal frequency `Low' Tone nominal frequency Start of Tone Alert signal to DET high time (Tton) End of Tone Alert signal to DET high time (Ttoff) DET high time to ensure interrupt status bit in CASDET goes high (TqCAS) To Ensure Detection `Low' Tone frequency tolerance `High' Tone frequency tolerance Level (per tone) 2750Hz tone level wrt 2130Hz tone level Signal to Noise ratio Dual Tone burst duration for DET output Dual Tone burst duration to ensure interrupt status bit goes high. To Ensure non-detection `Low' Tone frequency tolerance `High' Tone frequency tolerance Level (total) Dual Tone burst duration
Notes 10 10
Min. -30.0 -10.0 1.8 14.0 40.0 30.0 Min.
Typ. 25.0 Typ. 2130 2750 55.0
Max. 0 -36.0 6.0 3.5 0 10.0 20.0 -10.0 40.0 30.0 15.0 Max.
Unit dBm dBm dB % dB dB dB dB ms ms ms ms ms ms ms Units Hz Hz ms ms ms
14 14 14 14,15
Notes
16
0.5 8.0
17.0 45.0 to 80.0 0.5 0.5 -2.2 +6.0
16
-40.0 -6.0 20.0 75 75
85 to 120
% % dBV dB dB ms ms
75 95 -46.0 45.0
Hz Hz dBV ms
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FSK Receiver Transmission Rate V23 Mark (logical 1) frequency V23 Space (logical 0) frequency Bell202 Mark (logical 1) frequency Bell202 Space (logical 0) frequency Valid input level range Acceptable twist (mark level wrt space level) V23 Bell202 Acceptable Signal to Noise ratio V23 Bell202 Level Detector `on' threshold level Level Detector `off' to `on' time (Fig 7b Teon) Level Detector `on' to `off' time (Fig 7b Teoff) Analogue to Digital Convertor (excluding track/hold) Resolution Conversion Time Integral non-linearity Differential non-linearity Zero Error VRef Generator Power Up Time (after enable) VRef Generator Voltage Output RC Oscillator Frequency Start-up time
Notes
Min. 1188 1280 2068 1188 2178 -40.0 -6.0 -10.0
Typ. 1200 1300 2100 1200 2200
Max. 1212 1320 1320 1212 2222 -8.0 +6.0 +10.0
Units Baud Hz Hz Hz Hz dBV dB dB dB dB dBV ms ms Units
15 15
20.0 30.0 -40.0 25.0 8.0
Notes
Min.
Typ. 10 156
Max.
17 18 19 -20
2 1 20 100
Bits System Clock Cycles LSBs LSBs mV s V Units MHz s
2.25 Notes Min. 2.5
2.5 Typ. 5.5 0.5
2.75 Max. 9.5 4
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Notes:
1. At AVDD = DVDD = 3.3V and Tamb = 25C, not including any current drawn from the CMX850 pins by external circuitry other than X1, X2, C8, C9, C10, and C11. 2. All logic inputs at DVSS except for RESETN, HT, RT and inputs which are at DVDD. 3. Continuous conversion at maximum rate, with internal reference and threshold compare. 4. Excluding RESETN, RD, RT, HD and HT pins. 5. % carrier frequency accuracy is the same as XTAL/CLOCK % frequency accuracy. 6. Tx signal % baud or bit rate accuracy is the same as XTAL/CLOCK % frequency accuracy. 7. Measured across the line using the components recommended in section 1.4.4 with Tx Level Control gain set to 0dB, at AVDD = 3.3V (levels are proportional to AVDD). Level measurements for all modem modes are performed with random transmitted data and without any guard tone. 0dBm = 775mVrms. DTMF twist set to +2.0dB. 8. Measured on the 2-wire line using the line interface circuits described in section 1.4.4 with the Tx line signal level set to -10dBm for FSK or single tones, -6dBm and -8dBm for DTMF tones. Excludes any distortion due to external components required for line coupling. 9. These are the bit and baud rates of the line signal, the acceptable tolerance is 0.01%. 10. Rx 2-wire line signal level assuming 1dB loss in line coupling components with Rx Gain Control block set to 0dB and external components recommended in section 1.4.4. 11. Thresholds and times measured with continuous binary `1' for all FSK modes. Fixed compromise line equaliser enabled. Signal switched between off and -33dBm. 12. `Typical' value refers to 2100Hz or 2225Hz signal switched between off and -33dBm. Times measured with respect to the received line signal. 13. `Typical' values refers to 400Hz signal switched between off and -33dBm. 14. Referenced to DTMF tone of lower amplitude. 15. Flat Gaussian Noise in 300-3400Hz band. 16. This depends upon the Tone Detect Window Control Bits. (see section 1.5.13) 17. Actual Time dependant on the clock frequency selected and XTAL used for the System Clock. 18. Integral non-linearity is defined as the width difference between an actual code midpoint and the line of best fit through all code midpoints, divided by the width of an ideal LSB. 19. Differential non-linearity is defined as the difference between adjacent code midpoints and the width of an ideal LSB, divided by the width of an ideal LSB. 20. Increased by 12TCLCL when a "stretch" cycle is selected.
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4 3.5 3 2.5 Vin 2 1.5 1 0.5 0 2.5 3 3.5 4 DVdd 4.5
Vthi Vtlo 5 5.5
Figure 16 Typical Schmitt Trigger Input Voltage Thresholds vs. DVDD
0 -10 -20 -30 dBm -40 -50 -60 -70 10 100 1000 Hz 10000 100000 Bell 202
Figure 17 Maximum Out of Band Tx Line Energy Limits (see note 8)
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1.7.1.3 Operating Characteristics (continued) EXTERNAL PROGRAM MEMORY READ CYCLE
TSHSL TAVSL
CSN1
TSHSL TAVSL
TSLIV TSLSH TSLAZ TSLIV TSLSH TSLAZ TSXIX TSXIZ
OEN D7-0 A15-0
INSTR. IN
TSXIX
INSTR. IN
TSXIZ
TAVIV
EXTERNAL DATA READ CYCLE
TAVSL2
CSN1/2/3
TAVSL2 TSHSL2
TSLDV TSLSH2 TSLDV TSLSH2 TSXDX TSXDZ
OEN D7-0 A15-0
INSTR. IN
TSXDX
DATA IN
TSXDZ
TAVDV
EXTERNAL DATA WRITE CYCLE
TAVSL2
CSN1/2/3
TAVWL TWLSL
TSLSH2 TSHWH TWLWH TSHQX
WEN D7-0 A15-0
INSTR. IN
DATA OUT
TQVSL
Figure 18 Non-Multiplexed Memory Interface Timing Diagrams
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1.7.1.3 Operating Characteristics (continued) EXTERNAL PROGRAM MEMORY READ CYCLE
TLHLL
ALE
TSHSL TAVSL TSLIV TSLSH TSLIV TSLSH TSXIX TSXIZ
CSN1
TSHSL TAVSL
OEN
TAVLL TLLAX TSXIX
INSTR. IN
TSXIZ
A7-0 A15-8
INSTR. IN
TAVIV
EXTERNAL DATA READ CYCLE
TLHLL
ALE
TAVSL2
CSN1/2/3
TAVSL2 TSHSL2
TSLDV TSLSH2 TSLDV TSLSH2 TSXDX TSXDZ
OEN
TAVLL TLLAX
TSXDX
DATA IN
TSXDZ
A7-0 A15-8
INSTR. IN
TAVDV
EXTERNAL DATA WRITE CYCLE
TLHLL
ALE
TAVSL2
CSN1/2/3
TAVWL TWLSL
TSLSH2 TSHWH TWLWH TSHQX
DATA OUT
WEN
TAVLL TLLAX TQVSL
A7-0 A15-8
INSTR. IN
Figure 19 Multiplexed Memory Interface Timing Diagrams
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1.7.1.3 Operating Characteristics (continued) For the following conditions unless otherwise specified: Pin capacitance = 50pF VDD = 3.0V to 3.6V, Tamb = - 40C to +85C Symbol TCLCL TAVDV TAVIV TAVLL TAVSL TAVSL2 TAVWL TLHLL TLLAX TQVSL TSHQX TSHSL TSHSL2 TSHWH TSLAZ TSLDV TSLIV TSLSH TSLSH2 TSXDX TSXDZ TSXIX TSXIZ TWLSL TWLW H Parameter Oscillator period Address valid to valid data in Address valid to valid instruction in Address valid to ALE low Address valid to CSN1 or OEN low (instruction) Address valid to CSN1/2/3 or OEN low (data) Address valid to WEN low ALE pulse width Address hold after ALE low Data valid to CSN1/2/3 low Data hold after CSN1/2/3 high CSN1 or OEN high (instruction) CSN1/2/3 or OEN high (data) WEN hold after CSN1/2/3 high CSN1 or OEN low to address float CSN1/2/3 or OEN to valid data in CSN1 or OEN to valid instruction in CSN1 or OEN pulse width (instruction) CSN1/2/3 or OEN pulse width (data) Data hold after CSN1/2/3 or OEN transition Data float after CSN1/2/3 or OEN transition Instruction hold after CSN1 or OEN transition Instruction float after CSN1 or OEN transition WEN low to CSN1/2/3 low WEN pulse width 20 2TCLCL-40 10TCLCL-40 0 TCLCL-25 ns ns 20 3TCLCL-40 6TCLCL-40 0 2TCLCL-60 20 TCLCL-40 2TCLCL-130 4TCLCL-130 2TCLCL-130 2TCLCL-40 TCLCL-30 2TCLCL-50 2TCLCL-50 3TCLCL-40 5TCLCL-40 2TCLCL-40 10 5TCLCL-175 3TCLCL-115 20 Notes Min. 80 9TCLCL-175 5TCLCL-115 Max. Units ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
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1.7.2
Packaging
Figure 20 100-pin LQFP (L8) Mechanical Outline: Order as part no. CMX850L8
Handling precautions: This product includes input protection, however, precautions should be taken to prevent device damage from electro-static discharge. CML does not assume any responsibility for the use of any circuitry described. No IPR or circuit patent licences are implied. CML reserves the right at any time without notice to change the said circuitry and this product specification. CML has a policy of testing every product shipped using calibrated test equipment to ensure compliance with this product specification. Specific testing of all circuit parameters is not necessarily performed.
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